linux-kernel - Re: [PATCH] usb: dwc3: make USB_DWC3

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YCEnE4/Pf8P/CCID@kroah.com>
Date:   Mon, 8 Feb 2021 12:57:07 +0100
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     taehyun cho <taehyun.cho@...sung.com>
Cc:     balbi@...nel.org, linux-usb@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] usb: dwc3: make USB_DWC3_EXYNOS independent

On Mon, Feb 08, 2021 at 08:45:38PM +0900, taehyun cho wrote:
> 'ARCH_EXYNOS' is no more used.

I do not understand this sentance.  I see it used in many places in the
kernel tree still, is it being removed?

And if so, as of what commit is this true?

> 'USB_DWC3_EXYNOS' is glue layer
> which can be used with Synopsys DWC3 controller on Exynos SoCs.
> 'USB_DWC3_EXYNOS' can be used from Exynos5 to Exynos9.

This is fine, but the help text doesn't show this, why not put that
information there?

> 
> Signed-off-by: taehyun cho <taehyun.cho@...sung.com>
> ---
>  drivers/usb/dwc3/Kconfig | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> index 2133acf8ee69..dc2f92ac8ef6 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -67,10 +67,10 @@ config USB_DWC3_OMAP
>  
>  config USB_DWC3_EXYNOS
>  	tristate "Samsung Exynos Platform"
> -	depends on (ARCH_EXYNOS || COMPILE_TEST) && OF
> +	depends on (USB_DWC3 || COMPILE_TEST) && OF
>  	default USB_DWC3
>  	help
> -	  Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
> +	  Exynos SoCs chip with one DesignWare Core USB3 IP inside,

This does not make much sense anymore, can you reword it?

thanks,

greg k-h