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Message-ID: <CAPv3WKfs3mYsM5omSSF+yZjo_s8-qFh9Yrr8JqB8FpvmPSvWdQ@mail.gmail.com>
Date: Wed, 10 Feb 2021 15:02:00 +0100
From: Marcin Wojtas <mw@...ihalf.com>
To: Kostya Porotchkin <kostap@...vell.com>
Cc: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Vladimir Vid <vladimir.vid@...tura.hr>, tmn505@...il.com,
luka.kovacic@...tura.hr,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Grégory Clement <gregory.clement@...tlin.com>,
Andrew Lunn <andrew@...n.ch>, Rob Herring <robh+dt@...nel.org>,
vkoul@...nel.org, kishon@...com,
Miquèl Raynal <miquel.raynal@...tlin.com>,
Grzegorz Jaszczyk <jaz@...ihalf.com>, nadavh@...vell.com,
Stefan Chulski <stefanc@...vell.com>,
Ben Peled (בן פלד) <bpeled@...vell.com>
Subject: Re: [PATCH v5 4/5] dts: marvell: Enable 10G interfaces on 9130-DB and
9131-DB boards
śr., 10 lut 2021 o 14:16 <kostap@...vell.com> napisał(a):
>
> From: Stefan Chulski <stefanc@...vell.com>
>
> This patch enables eth0 10G interface on CN9130-DB paltforms and
> eth0 10G and eth3 10G interfaces on CN9131-DB.
Thank you.
Reviewed-by: Marcin Wojtas <mw@...ihalf.com>
>
> Signed-off-by: Stefan Chulski <stefanc@...vell.com>
> Signed-off-by: Konstantin Porotchkin <kostap@...vell.com>
> ---
> arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 +-
> arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
> index 8de3a552b806..97c74b81fd78 100644
> --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
> +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
> @@ -125,7 +125,7 @@
>
> /* SLM-1521-V2, CON9 */
> &cp0_eth0 {
> - status = "disabled";
> + status = "okay";
> phy-mode = "10gbase-kr";
> /* Generic PHY, providing serdes lanes */
> phys = <&cp0_comphy4 0>;
> diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
> index 82471a83ad6d..f2e4d3a6a4f8 100644
> --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
> +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
> @@ -84,7 +84,7 @@
>
> /* CON50 */
> &cp1_eth0 {
> - status = "disabled";
> + status = "okay";
> phy-mode = "10gbase-kr";
> /* Generic PHY, providing serdes lanes */
> phys = <&cp1_comphy4 0>;
> --
> 2.17.1
>
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