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Message-ID: <YCUsab1NaHxNG7sU@rocinante>
Date: Thu, 11 Feb 2021 14:08:57 +0100
From: Krzysztof WilczyĆski <kw@...ux.com>
To: Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>
Cc: dmaengine@...r.kernel.org, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org, Vinod Koul <vkoul@...nel.org>,
Dan Williams <dan.j.williams@...el.com>,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH v5 09/15] dmaengine: dw-edma: Improve the linked list and
data blocks definition
Hi Gustavo,
> In the previous implementation the driver assumes that only existed 2
> memory spaces that would be equal distributed amount the write/read
> channels.
What do you think about:
In the previous implementation the driver assumed that there existed
only two memory spaces that would equally distribute the amount of
read/write channels.
> This might not be the case on some other implementations, therefore this
> patches changes this requirement so that each write/read channel has
[...]
Probably "patch" here.
Krzysztof
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