linux-kernel - Re: [PATCH v1 18/18] arm64: dts: imx8mq: Add node to G2 hardware

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Message-ID: <b7338896a344ac06f41d782b6b56db227e359348.camel@collabora.com>
Date:   Wed, 17 Feb 2021 17:43:53 -0300
From:   Ezequiel Garcia <ezequiel@...labora.com>
To:     Benjamin Gaignard <benjamin.gaignard@...labora.com>,
        p.zabel@...gutronix.de, mchehab@...nel.org, robh+dt@...nel.org,
        shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de,
        festevam@...il.com, linux-imx@....com, gregkh@...uxfoundation.org,
        mripard@...nel.org, paul.kocialkowski@...tlin.com, wens@...e.org,
        jernej.skrabec@...l.net, krzk@...nel.org, shengjiu.wang@....com,
        adrian.ratiu@...labora.com, aisheng.dong@....com, peng.fan@....com,
        Anson.Huang@....com, hverkuil-cisco@...all.nl
Cc:     linux-media@...r.kernel.org, linux-rockchip@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, devel@...verdev.osuosl.org,
        kernel@...labora.com
Subject: Re: [PATCH v1 18/18] arm64: dts: imx8mq: Add node to G2 hardware

On Wed, 2021-02-17 at 09:03 +0100, Benjamin Gaignard wrote:
> Split VPU node in two: one for G1 and one for G2 since they are
> different hardware blocks.
> 
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@...labora.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 +++++++++++++++++------
>  1 file changed, 33 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index d9d9efc8592d..3cab3f0b9131 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1287,17 +1287,16 @@ vpu_reset: vpu-reset@...20000 {
>                         #reset-cells = <1>;
>                 };
>  
> -               vpu: video-codec@...00000 {
> +               vpu_g1: video-codec@...00000 {
>                         compatible = "nxp,imx8mq-vpu";
> -                       reg = <0x38300000 0x10000>,
> -                             <0x38310000 0x10000>;
> -                       reg-names = "g1", "g2";
> -                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> -                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> -                       interrupt-names = "g1", "g2";
> +                       reg = <0x38300000 0x10000>;
> +                       reg-names = "g1";
> +                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "g1";
>                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> -                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> -                       clock-names = "g1", "g2";
> +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> +                                <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> +                       clock-names = "g1", "g2", "bus";

How come the G1 block needs the G2 clock?

>                         assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
>                                           <&clk IMX8MQ_CLK_VPU_G2>,
>                                           <&clk IMX8MQ_CLK_VPU_BUS>,
> @@ -1306,12 +1305,36 @@ vpu: video-codec@...00000 {
>                                                  <&clk IMX8MQ_VPU_PLL_OUT>,
>                                                  <&clk IMX8MQ_SYS1_PLL_800M>,
>                                                  <&clk IMX8MQ_VPU_PLL>;
> -                       assigned-clock-rates = <600000000>, <600000000>,
> +                       assigned-clock-rates = <600000000>, <300000000>,
>                                                <800000000>, <0>;
>                         resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G1>;
>                         power-domains = <&pgc_vpu>;
>                 };
>  
> +               vpu_g2: video-codec@...10000 {
> +                       compatible = "nxp,imx8mq-vpu-g2";
> +                       reg = <0x38310000 0x10000>;
> +                       reg-names = "g2";
> +                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "g2";
> +                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,

Ditto, the G2 block needs the G1 clock?

Thanks,
Ezequiel