[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20210217204444.GA505189@gmail.com>
Date: Wed, 17 Feb 2021 21:44:44 +0100
From: Ingo Molnar <mingo@...nel.org>
To: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: linux-kernel@...r.kernel.org,
Peter Zijlstra <a.p.zijlstra@...llo.nl>,
Arnaldo Carvalho de Melo <acme@...radead.org>,
Thomas Gleixner <tglx@...utronix.de>
Subject: [GIT PULL] Performance events updates for v5.12
Linus,
Please pull the latest perf/core git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-core-2021-02-17
# HEAD: 8bcfdd7cad3dffdd340f9a79098cbf331eb2cd53 Merge branch 'perf/kprobes' into perf/core, to pick up finished branch
The performance event updates for v5.12 are:
- Add CPU-PMU support for Intel Sapphire Rapids CPUs
- Extend the perf ABI with PERF_SAMPLE_WEIGHT_STRUCT, to offer two-parameter
sampling event feedback. Not used yet, but is intended for Golden Cove
CPU-PMU, which can provide both the instruction latency and the cache
latency information for memory profiling events.
- Remove experimental, default-disabled perfmon-v4 counter_freezing support
that could only be enabled via a boot option. The hardware is hopelessly
broken, we'd like to make sure nobody starts relying on this, as it would
only end in tears.
- Fix energy/power events on Intel SPR platforms
- Simplify the uprobes resume_execution() logic
- Misc smaller fixes.
Thanks,
Ingo
------------------>
Jim Mattson (1):
perf/x86/kvm: Add Cascade Lake Xeon steppings to isolation_ucodes[]
Kan Liang (5):
perf/core: Add PERF_SAMPLE_WEIGHT_STRUCT
perf/x86/intel: Factor out intel_update_topdown_event()
perf/x86/intel: Filter unsupported Topdown metrics event
perf/x86/intel: Add perf core PMU support for Sapphire Rapids
perf/x86/intel: Support CPUID 10.ECX to disable fixed counters
Like Xu (1):
x86/perf: Use static_call for x86_pmu.guest_get_msrs
Masami Hiramatsu (1):
x86/kprobes: Do not decode opcode in resume_execution()
Peter Zijlstra (1):
perf/intel: Remove Perfmon-v4 counter_freezing support
Steve Wahl (2):
perf/x86/intel/uncore: Store the logical die id instead of the physical die id.
perf/x86/intel/uncore: With > 8 nodes, get pci bus die id from NUMA info
Zhang Rui (3):
perf/x86/rapl: Add msr mask support
perf/x86/rapl: Only check lower 32bits for RAPL energy counters
perf/x86/rapl: Fix psys-energy event on Intel SPR platform
Documentation/admin-guide/kernel-parameters.txt | 6 -
arch/powerpc/perf/core-book3s.c | 2 +-
arch/x86/events/core.c | 28 +-
arch/x86/events/intel/core.c | 547 +++++++++++++++---------
arch/x86/events/intel/ds.c | 131 +++++-
arch/x86/events/intel/uncore.c | 58 +--
arch/x86/events/intel/uncore.h | 5 +-
arch/x86/events/intel/uncore_snb.c | 2 +-
arch/x86/events/intel/uncore_snbep.c | 114 +++--
arch/x86/events/perf_event.h | 21 +-
arch/x86/events/probe.c | 7 +-
arch/x86/events/probe.h | 7 +-
arch/x86/events/rapl.c | 34 +-
arch/x86/include/asm/kprobes.h | 11 +-
arch/x86/include/asm/perf_event.h | 24 +-
arch/x86/kernel/kprobes/core.c | 168 ++++----
include/linux/perf_event.h | 4 +-
include/uapi/linux/perf_event.h | 54 ++-
kernel/events/core.c | 11 +-
19 files changed, 801 insertions(+), 433 deletions(-)
Powered by blists - more mailing lists