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Message-ID: <2BA0A0C7-DA37-486B-B12F-C485F1000F8E@aosc.io>
Date: Thu, 18 Feb 2021 17:21:16 +0800
From: Icenowy Zheng <icenowy@...c.io>
To: Tobias Schramm <t.schramm@...jaro.org>,
Maxime Ripard <maxime@...no.tech>
CC: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...l.net>,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output
于 2021年2月18日 GMT+08:00 下午5:18:39, Tobias Schramm <t.schramm@...jaro.org> 写到:
>Hi Icenowy,
>
> > We have introducee SDM-based accurate audio PLL on several
>> other SoCs. Some people is quite sensitive about audio-related
>things.
> >
>While it is possible to support 24MHz * 128 / 25 / 5 = 24.576MHz
>without
>delta sigma modulation, matching 22.5792MHz is indeed not possible. I
>read you'd prefer me to use SDM like the other SoCs though? Shall I
>send
>a v2 utilizing SDM?
Yes, I think so.
>
>Cheers,
>Tobias
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