linux-kernel - Re: [PATCH 06/13] arm64: dts: qcom: SC7280: Add rpmhcc clock controller node

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Message-ID: <f58070ee-ff00-f8c5-6459-782562e903e5@codeaurora.org>
Date:   Mon, 1 Mar 2021 22:57:06 +0530
From:   Taniya Das <tdas@...eaurora.org>
To:     Stephen Boyd <swboyd@...omium.org>,
        Rajendra Nayak <rnayak@...eaurora.org>, agross@...nel.org,
        bjorn.andersson@...aro.org, robh+dt@...nel.org
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 06/13] arm64: dts: qcom: SC7280: Add rpmhcc clock
 controller node

Hello Stephen,

Thanks for the review.

On 2/23/2021 1:13 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2021-02-11 23:28:43)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 7848e88..10851e7 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -6,6 +6,7 @@
>>    */
>>   
>>   #include <dt-bindings/clock/qcom,gcc-sc7280.h>
>> +#include <dt-bindings/clock/qcom,rpmh.h>
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>>   
>> @@ -29,6 +30,42 @@
>>                          clock-frequency = <32000>;
>>                          #clock-cells = <0>;
>>                  };
>> +
>> +               pcie_0_pipe_clk: pcie-0-pipe-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               pcie_1_pipe_clk: pcie-1-pipe-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
> 
> Shouldn't these come from the phys? Why are they being added here?
> 

Once the phys are added, these could be replaced, that was the reason to 
add them.

>>          };
>>   
>>          reserved_memory: reserved-memory {
>> @@ -174,6 +211,17 @@
>>                  gcc: clock-controller@...000 {
>>                          compatible = "qcom,gcc-sc7280";
>>                          reg = <0 0x00100000 0 0x1f0000>;
>> +                       clocks = <&rpmhcc RPMH_CXO_CLK>,
>> +                                <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
>> +                                <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
>> +                                <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
>> +                                <&ufs_phy_tx_symbol_0_clk>,
>> +                                <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
> 
> If the phys aren't ready then <0> should work. Unless something goes
> wrong?
>

Nothing would go wrong if we add <0>, but wanted them to be replaced 
once the support is added.


>> +                       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
>> +                                     "pcie_0_pipe_clk", "pcie_1_pipe-clk",
>> +                                     "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
>> +                                     "ufs_phy_tx_symbol_0_clk",
>> +                                     "usb3_phy_wrapper_gcc_usb30_pipe_clk";
>>                          #clock-cells = <1>;
>>                          #reset-cells = <1>;
>>                          #power-domain-cells = <1>;
>> @@ -325,6 +373,13 @@
>>                                            <SLEEP_TCS   3>,
>>                                            <WAKE_TCS    3>,
>>                                            <CONTROL_TCS 1>;
>> +
>> +                       rpmhcc: qcom,rpmhcc {
> 
> rpmhcc: clock-controller {
> 

Will update in the next patch.

>> +                               compatible = "qcom,sc7280-rpmh-clk";
>> +                               clocks = <&xo_board>;
>> +                               clock-names = "xo";
>> +                               #clock-cells = <1>;
>> +                       };
>>                  };
>>          };
>>

-- 
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