linux-kernel - Re: [PATCH 06/13] arm64: dts: qcom: SC7280: Add rpmhcc clock controller node

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 03 Mar 2021 00:21:25 -0800
From:   Stephen Boyd <swboyd@...omium.org>
To:     Rajendra Nayak <rnayak@...eaurora.org>,
        Taniya Das <tdas@...eaurora.org>, agross@...nel.org,
        bjorn.andersson@...aro.org, robh+dt@...nel.org
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 06/13] arm64: dts: qcom: SC7280: Add rpmhcc clock controller node

Quoting Taniya Das (2021-03-01 09:27:06)
> On 2/23/2021 1:13 PM, Stephen Boyd wrote:
> > Quoting Rajendra Nayak (2021-02-11 23:28:43)
> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> +               usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
> >> +                       compatible = "fixed-clock";
> >> +                       clock-frequency = <1000>;
> >> +                       #clock-cells = <0>;
> >> +               };
> > 
> > Shouldn't these come from the phys? Why are they being added here?
> > 
> 
> Once the phys are added, these could be replaced, that was the reason to 
> add them.
> 
> >>          };
> >>   
> >>          reserved_memory: reserved-memory {
> >> @@ -174,6 +211,17 @@
> >>                  gcc: clock-controller@...000 {
> >>                          compatible = "qcom,gcc-sc7280";
> >>                          reg = <0 0x00100000 0 0x1f0000>;
> >> +                       clocks = <&rpmhcc RPMH_CXO_CLK>,
> >> +                                <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> >> +                                <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
> >> +                                <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
> >> +                                <&ufs_phy_tx_symbol_0_clk>,
> >> +                                <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
> > 
> > If the phys aren't ready then <0> should work. Unless something goes
> > wrong?
> >
> 
> Nothing would go wrong if we add <0>, but wanted them to be replaced 
> once the support is added.

Please use <0> to indicate that it's missing. Otherwise we may never
realize that we should connect it up later.