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Message-Id: <20210303200253.1827553-5-atish.patra@wdc.com>
Date: Wed, 3 Mar 2021 12:02:52 -0800
From: Atish Patra <atish.patra@....com>
To: linux-kernel@...r.kernel.org
Cc: Atish Patra <atish.patra@....com>,
Anup Patel <anup@...infault.org>,
Bin Meng <bin.meng@...driver.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alistair Francis <alistair.francis@....com>,
Anup Patel <anup.patel@....com>,
Björn Töpel <bjorn@...nel.org>,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Rob Herring <robh+dt@...nel.org>, Conor.Dooley@...rochip.com,
Daire McNamara <daire.mcnamara@...rochip.com>,
Ivan.Griffin@...rochip.com, Lewis.Hanly@...rochip.com
Subject: [PATCH v4 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC
Enable Microchip PolarFire ICICLE soc config in defconfig.
It allows the default upstream kernel to boot on PolarFire ICICLE board.
Signed-off-by: Atish Patra <atish.patra@....com>
Reviewed-by: Anup Patel <anup@...infault.org>
Reviewed-by: Bin Meng <bin.meng@...driver.com>
---
arch/riscv/configs/defconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 6c0625aa96c7..1f2be234b11c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -16,6 +16,7 @@ CONFIG_EXPERT=y
CONFIG_BPF_SYSCALL=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
+CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_JUMP_LABEL=y
@@ -82,6 +83,9 @@ CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC=y
CONFIG_MMC_SPI=y
CONFIG_RTC_CLASS=y
--
2.25.1
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