[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1a78ad4a-bb6c-cb68-019d-d6de54c2dc38@codeaurora.org>
Date: Fri, 5 Mar 2021 11:14:08 +0530
From: Rajendra Nayak <rnayak@...eaurora.org>
To: Stephen Boyd <swboyd@...omium.org>, agross@...nel.org,
bjorn.andersson@...aro.org, robh+dt@...nel.org
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, satya priya <skakit@...eaurora.org>
Subject: Re: [PATCH v2 12/14] arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter
device for SC7280
On 3/4/2021 5:42 AM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2021-03-03 04:17:56)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index fe4fdb9..aa6f847 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -239,6 +239,25 @@
>> interrupt-controller;
>> };
>>
>> + spmi_bus: spmi@...0000 {
>> + compatible = "qcom,spmi-pmic-arb";
>> + reg = <0 0x0c440000 0 0x1100>,
>> + <0 0x0c600000 0 0x2000000>,
>> + <0 0x0e600000 0 0x100000>,
>> + <0 0x0e700000 0 0xa0000>,
>> + <0 0x0c40a000 0 0x26000>;
>> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
>> + interrupt-names = "periph_irq";
>> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
>> + qcom,ee = <0>;
>> + qcom,channel = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>
> I see the binding says these should be 2 instead of 1 but I suspect that
> is incorrect.
yeah looks like the bindings need to be fixed
>
>> + interrupt-controller;
>> + #interrupt-cells = <4>;
>> + cell-index = <0>;
>
> Is cell-index used? Please remove as I don't see it used anywhere and
> not in the binding.
I'll drop it. thanks
>
>> + };
>> +
>> tlmm: pinctrl@...0000 {
>> compatible = "qcom,sc7280-pinctrl";
>> reg = <0 0x0f100000 0 0x1000000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Powered by blists - more mailing lists