linux-kernel - Re: [PATCH v6 5/9] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate

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Message-ID: <CAL9mu0+Uh84UGQ-1EW4+eVE1cFxuxJxLTLAa0rgJ_5C2pchUgA@mail.gmail.com>
Date:   Wed, 10 Mar 2021 19:43:05 +0800
From:   dillon min <dillon.minfei@...il.com>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     Dave Airlie <airlied@...ux.ie>,
        Alexandre Torgue <alexandre.torgue@...com>,
        Andy Shevchenko <andy.shevchenko@...il.com>,
        Mark Brown <broonie@...nel.org>,
        Daniel Vetter <daniel@...ll.ch>,
        Linus Walleij <linus.walleij@...aro.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Michael Turquette <mturquette@...libre.com>,
        Noralf Trønnes <noralf@...nnes.org>,
        p.zabel@...gutronix.de, Rob Herring <robh+dt@...nel.org>,
        Sam Ravnborg <sam@...nborg.org>, thierry.reding@...il.com,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-spi <linux-spi@...r.kernel.org>,
        linux-stm32@...md-mailman.stormreply.com,
        "open list:DRM PANEL DRIVERS" <dri-devel@...ts.freedesktop.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        Hua Dillon <dillonhua@...il.com>
Subject: Re: [PATCH v6 5/9] clk: stm32: Fix stm32f429's ltdc driver hang in
 set clock rate

still need more expert to review, so just a gentle ping for this patch

On Wed, May 27, 2020 at 4:35 PM Stephen Boyd <sboyd@...nel.org> wrote:
>
> Quoting dillon.minfei@...il.com (2020-05-27 00:27:29)
> > From: dillon min <dillon.minfei@...il.com>
> >
> > This is due to misuse \u2018PLL_VCO_SAI' and'PLL_SAI' in clk-stm32f4.c
> > 'PLL_SAI' is 2, 'PLL_VCO_SAI' is 7(defined in
> > include/dt-bindings/clock/stm32fx-clock.h).
> >
> > 'post_div' point to 'post_div_data[]', 'post_div->pll_num'
> > is PLL_I2S or PLL_SAI.
> >
> > 'clks[PLL_VCO_SAI]' has valid 'struct clk_hw* ' return
> > from stm32f4_rcc_register_pll() but, at line 1777 of
> > driver/clk/clk-stm32f4.c, use the 'clks[post_div->pll_num]',
> > equal to 'clks[PLL_SAI]', this is invalid array member at that time.
> >
> > Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs")
> > Signed-off-by: dillon min <dillon.minfei@...il.com>
> > ---
>
> Acked-by: Stephen Boyd <sboyd@...nel.org>