| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAL9mu0LyFPjf+RLwet43zgcEnO9zhJJ=v1BsQqN8KxYta7Q=DQ@mail.gmail.com>
Date: Mon, 15 Jun 2020 18:05:56 +0800
From: dillon min <dillon.minfei@...il.com>
To: Alexandre Torgue <alexandre.torgue@...com>
Cc: Rob Herring <robh+dt@...nel.org>, p.zabel@...gutronix.de,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
thierry.reding@...il.com, Sam Ravnborg <sam@...nborg.org>,
Dave Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Andy Shevchenko <andy.shevchenko@...il.com>,
Noralf Trønnes <noralf@...nnes.org>,
Linus Walleij <linus.walleij@...aro.org>,
Mark Brown <broonie@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-spi <linux-spi@...r.kernel.org>,
linux-stm32@...md-mailman.stormreply.com,
"open list:DRM PANEL DRIVERS" <dri-devel@...ts.freedesktop.org>,
linux-clk <linux-clk@...r.kernel.org>,
Hua Dillon <dillonhua@...il.com>
Subject: Re: [PATCH v6 2/9] ARM: dts: stm32: Add pin map for ltdc & spi5 on
stm32f429-disco board
On Mon, Jun 15, 2020 at 5:45 PM Alexandre Torgue
<alexandre.torgue@...com> wrote:
>
> Hi Dillon
>
> On 5/27/20 9:27 AM, dillon.minfei@...il.com wrote:
> > From: dillon min <dillon.minfei@...il.com>
> >
> > This patch adds the pin configuration for ltdc and spi5 controller
> > on stm32f429-disco board.
> >
> > Signed-off-by: dillon min <dillon.minfei@...il.com>
> > ---
> > arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 67 ++++++++++++++++++++++++++++++++++
> > 1 file changed, 67 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
> > index 392fa143ce07..0eb107f968cd 100644
> > --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
> > +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
> > @@ -316,6 +316,73 @@
> > };
> > };
> >
> > + ltdc_pins_f429_disco: ltdc-1 {
>
> Sorry I missed this issue during review. I changed ltdc_pins_f429_disco
> by ltdc_pins_b when I applied your patch.
Okay, thanks for reviewing.
Regrades,
Dillon,
>
>
> Regards
> alex
>
> > + pins {
> > + pinmux = <STM32_PINMUX('C', 6, AF14)>,
> > + /* LCD_HSYNC */
> > + <STM32_PINMUX('A', 4, AF14)>,
> > + /* LCD_VSYNC */
> > + <STM32_PINMUX('G', 7, AF14)>,
> > + /* LCD_CLK */
> > + <STM32_PINMUX('C', 10, AF14)>,
> > + /* LCD_R2 */
> > + <STM32_PINMUX('B', 0, AF9)>,
> > + /* LCD_R3 */
> > + <STM32_PINMUX('A', 11, AF14)>,
> > + /* LCD_R4 */
> > + <STM32_PINMUX('A', 12, AF14)>,
> > + /* LCD_R5 */
> > + <STM32_PINMUX('B', 1, AF9)>,
> > + /* LCD_R6*/
> > + <STM32_PINMUX('G', 6, AF14)>,
> > + /* LCD_R7 */
> > + <STM32_PINMUX('A', 6, AF14)>,
> > + /* LCD_G2 */
> > + <STM32_PINMUX('G', 10, AF9)>,
> > + /* LCD_G3 */
> > + <STM32_PINMUX('B', 10, AF14)>,
> > + /* LCD_G4 */
> > + <STM32_PINMUX('D', 6, AF14)>,
> > + /* LCD_B2 */
> > + <STM32_PINMUX('G', 11, AF14)>,
> > + /* LCD_B3*/
> > + <STM32_PINMUX('B', 11, AF14)>,
> > + /* LCD_G5 */
> > + <STM32_PINMUX('C', 7, AF14)>,
> > + /* LCD_G6 */
> > + <STM32_PINMUX('D', 3, AF14)>,
> > + /* LCD_G7 */
> > + <STM32_PINMUX('G', 12, AF9)>,
> > + /* LCD_B4 */
> > + <STM32_PINMUX('A', 3, AF14)>,
> > + /* LCD_B5 */
> > + <STM32_PINMUX('B', 8, AF14)>,
> > + /* LCD_B6 */
> > + <STM32_PINMUX('B', 9, AF14)>,
> > + /* LCD_B7 */
> > + <STM32_PINMUX('F', 10, AF14)>;
> > + /* LCD_DE */
> > + slew-rate = <2>;
> > + };
> > + };
> > +
> > + spi5_pins: spi5-0 {
> > + pins1 {
> > + pinmux = <STM32_PINMUX('F', 7, AF5)>,
> > + /* SPI5_CLK */
> > + <STM32_PINMUX('F', 9, AF5)>;
> > + /* SPI5_MOSI */
> > + bias-disable;
> > + drive-push-pull;
> > + slew-rate = <0>;
> > + };
> > + pins2 {
> > + pinmux = <STM32_PINMUX('F', 8, AF5)>;
> > + /* SPI5_MISO */
> > + bias-disable;
> > + };
> > + };
> > +
> > dcmi_pins: dcmi-0 {
> > pins {
> > pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
> >
Powered by blists - more mailing lists