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Message-Id: <20210311070742.9318-11-yao.jin@linux.intel.com>
Date: Thu, 11 Mar 2021 15:07:25 +0800
From: Jin Yao <yao.jin@...ux.intel.com>
To: acme@...nel.org, jolsa@...nel.org, peterz@...radead.org,
mingo@...hat.com, alexander.shishkin@...ux.intel.com
Cc: Linux-kernel@...r.kernel.org, ak@...ux.intel.com,
kan.liang@...el.com, yao.jin@...el.com,
Jin Yao <yao.jin@...ux.intel.com>, hardware@...r.kernel.org
Subject: [PATCH v2 10/27] perf parse-events: Create two hybrid cache events
For cache events, they have pre-defined configs. The kernel needs
to know where the cache event comes from (e.g. from cpu_core pmu
or from cpu_atom pmu). But the perf type 'PERF_TYPE_HW_CACHE'
can't carry pmu information.
So the kernel introduces a new type 'PERF_TYPE_HW_CACHE_PMU'.
The new attr.config layout for PERF_TYPE_HW_CACHE_PMU is
0xDD00CCBBAA
AA: hardware cache ID
BB: hardware cache op ID
CC: hardware cache op result ID
DD: PMU type ID
Similar as hardware event, PMU type ID is retrieved from sysfs.
When enabling a hybrid cache event without specified pmu, such as,
'perf stat -e L1-dcache-loads -a', two events are created
automatically. One is for atom, the other is for core.
root@...-pwrt-002:~# ./perf stat -e L1-dcache-loads -vv -a -- sleep 1
Control descriptor is not initialized
------------------------------------------------------------
perf_event_attr:
type 7
size 120
config 0x400000000
sample_type IDENTIFIER
read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING
disabled 1
inherit 1
exclude_guest 1
------------------------------------------------------------
sys_perf_event_open: pid -1 cpu 0 group_fd -1 flags 0x8 = 3
sys_perf_event_open: pid -1 cpu 1 group_fd -1 flags 0x8 = 4
sys_perf_event_open: pid -1 cpu 2 group_fd -1 flags 0x8 = 5
sys_perf_event_open: pid -1 cpu 3 group_fd -1 flags 0x8 = 7
sys_perf_event_open: pid -1 cpu 4 group_fd -1 flags 0x8 = 8
sys_perf_event_open: pid -1 cpu 5 group_fd -1 flags 0x8 = 9
sys_perf_event_open: pid -1 cpu 6 group_fd -1 flags 0x8 = 10
sys_perf_event_open: pid -1 cpu 7 group_fd -1 flags 0x8 = 11
sys_perf_event_open: pid -1 cpu 8 group_fd -1 flags 0x8 = 12
sys_perf_event_open: pid -1 cpu 9 group_fd -1 flags 0x8 = 13
sys_perf_event_open: pid -1 cpu 10 group_fd -1 flags 0x8 = 14
sys_perf_event_open: pid -1 cpu 11 group_fd -1 flags 0x8 = 15
sys_perf_event_open: pid -1 cpu 12 group_fd -1 flags 0x8 = 16
sys_perf_event_open: pid -1 cpu 13 group_fd -1 flags 0x8 = 17
sys_perf_event_open: pid -1 cpu 14 group_fd -1 flags 0x8 = 18
sys_perf_event_open: pid -1 cpu 15 group_fd -1 flags 0x8 = 19
------------------------------------------------------------
perf_event_attr:
type 7
size 120
config 0xa00000000
sample_type IDENTIFIER
read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING
disabled 1
inherit 1
exclude_guest 1
------------------------------------------------------------
sys_perf_event_open: pid -1 cpu 16 group_fd -1 flags 0x8 = 20
sys_perf_event_open: pid -1 cpu 17 group_fd -1 flags 0x8 = 21
sys_perf_event_open: pid -1 cpu 18 group_fd -1 flags 0x8 = 22
sys_perf_event_open: pid -1 cpu 19 group_fd -1 flags 0x8 = 23
sys_perf_event_open: pid -1 cpu 20 group_fd -1 flags 0x8 = 24
sys_perf_event_open: pid -1 cpu 21 group_fd -1 flags 0x8 = 25
sys_perf_event_open: pid -1 cpu 22 group_fd -1 flags 0x8 = 26
sys_perf_event_open: pid -1 cpu 23 group_fd -1 flags 0x8 = 27
L1-dcache-loads: 0: 13103284 1002535421 1002535421
L1-dcache-loads: 1: 12995797 1002532807 1002532807
L1-dcache-loads: 2: 13428186 1002528572 1002528572
L1-dcache-loads: 3: 12913469 1002517437 1002517437
L1-dcache-loads: 4: 12857843 1002507079 1002507079
L1-dcache-loads: 5: 12812079 1002498279 1002498279
L1-dcache-loads: 6: 12829938 1002490010 1002490010
L1-dcache-loads: 7: 12807085 1002481860 1002481860
L1-dcache-loads: 8: 12907189 1002473181 1002473181
L1-dcache-loads: 9: 12823095 1002465895 1002465895
L1-dcache-loads: 10: 12892770 1002459322 1002459322
L1-dcache-loads: 11: 12789718 1002451607 1002451607
L1-dcache-loads: 12: 12838931 1002442632 1002442632
L1-dcache-loads: 13: 12803756 1002434133 1002434133
L1-dcache-loads: 14: 12840574 1002426060 1002426060
L1-dcache-loads: 15: 12799075 1002415964 1002415964
L1-dcache-loads: 0: 39394457 1002406287 1002406287
L1-dcache-loads: 1: 39372632 1002400502 1002400502
L1-dcache-loads: 2: 39405247 1002394865 1002394865
L1-dcache-loads: 3: 39400547 1002389099 1002389099
L1-dcache-loads: 4: 39410752 1002383106 1002383106
L1-dcache-loads: 5: 39402983 1002375365 1002375365
L1-dcache-loads: 6: 39388775 1002369374 1002369374
L1-dcache-loads: 7: 39408527 1002363344 1002363344
L1-dcache-loads: 206442789 16039660259 16039660259
L1-dcache-loads: 315183920 8019081942 8019081942
Performance counter stats for 'system wide':
206,442,789 cpu_core/L1-dcache-loads/
315,183,920 cpu_atom/L1-dcache-loads/
1.002751663 seconds time elapsed
type 7 is PERF_TYPE_HW_CACHE_PMU.
0x4 in 0x400000000 indicates the cpu_core pmu.
0xa in 0xa00000000 indicates the cpu_atom pmu.
Signed-off-by: Jin Yao <yao.jin@...ux.intel.com>
---
tools/perf/util/parse-events.c | 54 +++++++++++++++++++++++++++++++++-
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
index c6c76fc810a3..09e42245f71a 100644
--- a/tools/perf/util/parse-events.c
+++ b/tools/perf/util/parse-events.c
@@ -464,6 +464,48 @@ static void config_hybrid_attr(struct perf_event_attr *attr,
attr->config = attr->config | ((__u64)pmu_type << PERF_PMU_TYPE_SHIFT);
}
+static int create_hybrid_cache_event(struct list_head *list, int *idx,
+ struct perf_event_attr *attr, char *name,
+ struct list_head *config_terms,
+ struct perf_pmu *pmu)
+{
+ struct evsel *evsel;
+ __u32 type = attr->type;
+ __u64 config = attr->config;
+
+ config_hybrid_attr(attr, PERF_TYPE_HW_CACHE_PMU, pmu->type);
+ evsel = __add_event(list, idx, attr, true, name,
+ pmu, config_terms, false, NULL);
+ if (evsel)
+ evsel->pmu_name = strdup(pmu->name);
+ else
+ return -ENOMEM;
+
+ attr->type = type;
+ attr->config = config;
+ return 0;
+}
+
+static int add_hybrid_cache(struct list_head *list, int *idx,
+ struct perf_event_attr *attr, char *name,
+ struct list_head *config_terms,
+ bool *hybrid)
+{
+ struct perf_pmu *pmu;
+ int ret;
+
+ *hybrid = false;
+ perf_pmu__for_each_hybrid_pmu(pmu) {
+ *hybrid = true;
+ ret = create_hybrid_cache_event(list, idx, attr, name,
+ config_terms, pmu);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
int parse_events_add_cache(struct list_head *list, int *idx,
char *type, char *op_result1, char *op_result2,
struct parse_events_error *err,
@@ -474,7 +516,8 @@ int parse_events_add_cache(struct list_head *list, int *idx,
char name[MAX_NAME_LEN], *config_name;
int cache_type = -1, cache_op = -1, cache_result = -1;
char *op_result[2] = { op_result1, op_result2 };
- int i, n;
+ int i, n, ret;
+ bool hybrid;
/*
* No fallback - if we cannot get a clear cache type
@@ -534,6 +577,15 @@ int parse_events_add_cache(struct list_head *list, int *idx,
if (get_config_terms(head_config, &config_terms))
return -ENOMEM;
}
+
+ if (!perf_pmu__hybrid_exist())
+ perf_pmu__scan(NULL);
+
+ ret = add_hybrid_cache(list, idx, &attr, config_name ? : name,
+ &config_terms, &hybrid);
+ if (hybrid)
+ return ret;
+
return add_event(list, idx, &attr, config_name ? : name, &config_terms);
}
--
2.17.1
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