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Message-ID: <efa02319-2abf-4fb9-efec-13b6279f3d78@linux.intel.com>
Date: Mon, 15 Mar 2021 11:00:57 -0500
From: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
To: Vijendar Mukunda <Vijendar.Mukunda@....com>, broonie@...nel.org,
alsa-devel@...a-project.org
Cc: Alexander.Deucher@....com, Murali-krishna.Vemuri@....com,
Virendra-Pratap.Arya@....com, Liam Girdwood <lgirdwood@...il.com>,
Jaroslav Kysela <perex@...ex.cz>,
Takashi Iwai <tiwai@...e.com>,
Ravulapati Vishnu vardhan rao
<Vishnuvardhanrao.Ravulapati@....com>,
Arnd Bergmann <arnd@...db.de>,
Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
Chuhong Yuan <hslester96@...il.com>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3] ASoC: amd: add support for rt5682 codec in machine
driver
> +static int rt5682_clk_enable(struct snd_pcm_substream *substream)
> +{
> + int ret;
> + struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
> +
> + /*
> + * Set wclk to 48000 because the rate constraint of this driver is
> + * 48000. ADAU7002 spec: "The ADAU7002 requires a BCLK rate that is
> + * minimum of 64x the LRCLK sample rate." RT5682 is the only clk
> + * source so for all codecs we have to limit bclk to 64X lrclk.
> + */
> + clk_set_rate(rt5682_dai_wclk, 48000);
> + clk_set_rate(rt5682_dai_bclk, 48000 * 64);
> + ret = clk_prepare_enable(rt5682_dai_bclk);
> + if (ret < 0) {
> + dev_err(rtd->dev, "can't enable master clock %d\n", ret);
> + return ret;
> + }
> + return ret;
> +}
Out of curiosity, is there a reason why you use clk_prepare_enable() for
the bclk but not for the wclk?
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