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Message-ID: <87f41e68-3158-38f8-5e84-270ab184691b@amd.com>
Date:   Tue, 16 Mar 2021 19:07:09 +0530
From:   "Mukunda,Vijendar" <vijendar.mukunda@....com>
To:     Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>,
        broonie@...nel.org, alsa-devel@...a-project.org
Cc:     Alexander.Deucher@....com, Murali-krishna.Vemuri@....com,
        Virendra-Pratap.Arya@....com, Liam Girdwood <lgirdwood@...il.com>,
        Jaroslav Kysela <perex@...ex.cz>,
        Takashi Iwai <tiwai@...e.com>,
        Ravulapati Vishnu vardhan rao 
        <Vishnuvardhanrao.Ravulapati@....com>,
        Arnd Bergmann <arnd@...db.de>,
        Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
        Chuhong Yuan <hslester96@...il.com>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3] ASoC: amd: add support for rt5682 codec in machine
 driver



On 15/03/21 9:30 pm, Pierre-Louis Bossart wrote:
> 
>> +static int rt5682_clk_enable(struct snd_pcm_substream *substream)
>> +{
>> +    int ret;
>> +    struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
>> +
>> +    /*
>> +     * Set wclk to 48000 because the rate constraint of this driver is
>> +     * 48000. ADAU7002 spec: "The ADAU7002 requires a BCLK rate that is
>> +     * minimum of 64x the LRCLK sample rate." RT5682 is the only clk
>> +     * source so for all codecs we have to limit bclk to 64X lrclk.
>> +     */
>> +    clk_set_rate(rt5682_dai_wclk, 48000);
>> +    clk_set_rate(rt5682_dai_bclk, 48000 * 64);
>> +    ret = clk_prepare_enable(rt5682_dai_bclk);
>> +    if (ret < 0) {
>> +        dev_err(rtd->dev, "can't enable master clock %d\n", ret);
>> +        return ret;
>> +    }
>> +    return ret;
>> +}
> 
> Out of curiosity, is there a reason why you use clk_prepare_enable() for 
> the bclk but not for the wclk?These changes were shared by codec vendor as an initial patch.
We should use clk_prepare_enable() for wclk not for bclk.
We will update and share the new patch.



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