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Message-Id: <FB4E11A5-84D4-4DAF-889E-FAA1BCD2E66F@gmail.com>
Date: Tue, 16 Mar 2021 22:46:00 -0700
From: Nadav Amit <nadav.amit@...il.com>
To: "Longpeng (Mike, Cloud Infrastructure Service Product Dept.)"
<longpeng2@...wei.com>
Cc: David Woodhouse <dwmw2@...radead.org>,
Lu Baolu <baolu.lu@...ux.intel.com>,
Joerg Roedel <joro@...tes.org>, will@...nel.org,
alex.williamson@...hat.com, chenjiashang@...wei.com,
iommu@...ts.linux-foundation.org,
"Gonglei (Arei)" <arei.gonglei@...wei.com>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: A problem of Intel IOMMU hardware ?
> On Mar 16, 2021, at 8:16 PM, Longpeng (Mike, Cloud Infrastructure Service Product Dept.) <longpeng2@...wei.com> wrote:
>
> Hi guys,
>
> We find the Intel iommu cache (i.e. iotlb) maybe works wrong in a special
> situation, it would cause DMA fails or get wrong data.
>
> The reproducer (based on Alex's vfio testsuite[1]) is in attachment, it can
> reproduce the problem with high probability (~50%).
I saw Lu replied, and he is much more knowledgable than I am (I was just
intrigued by your email).
However, if I were you I would try also to remove some “optimizations” to
look for the root-cause (e.g., use domain specific invalidations instead
of page-specific).
The first thing that comes to my mind is the invalidation hint (ih) in
iommu_flush_iotlb_psi(). I would remove it to see whether you get the
failure without it.
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