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Message-Id: <20210317081725.28412-1-yuzihao@ict.ac.cn>
Date: Wed, 17 Mar 2021 16:17:25 +0800
From: Zihao Yu <yuzihao@....ac.cn>
To: paul.walmsley@...ive.com
Cc: palmer@...belt.com, aou@...s.berkeley.edu, yuzihao@....ac.cn,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH] riscv,entry: fix misaligned base for excp_vect_table
* In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.
Signed-off-by: Zihao Yu <yuzihao@....ac.cn>
---
arch/riscv/kernel/entry.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 744f3209c..76274a4a1 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -447,6 +447,7 @@ ENDPROC(__switch_to)
#endif
.section ".rodata"
+ .align LGREG
/* Exception vector table */
ENTRY(excp_vect_table)
RISCV_PTR do_trap_insn_misaligned
--
2.20.1
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