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Date: Wed, 17 Mar 2021 14:00:35 +0530
From: Anup Patel <anup@...infault.org>
To: Zihao Yu <yuzihao@....ac.cn>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
linux-riscv <linux-riscv@...ts.infradead.org>,
"linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] riscv,entry: fix misaligned base for excp_vect_table
On Wed, Mar 17, 2021 at 1:48 PM Zihao Yu <yuzihao@....ac.cn> wrote:
>
> * In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
> base of the table is not 8-byte aligned, loading an entry in the table
> will raise a misaligned exception. Although such exception will be
> handled by opensbi/bbl, this still causes performance degradation.
>
> Signed-off-by: Zihao Yu <yuzihao@....ac.cn>
Looks good to me.
Reviewed-by: Anup Patel <anup@...infault.org>
Regards,
Anup
> ---
> arch/riscv/kernel/entry.S | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 744f3209c..76274a4a1 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -447,6 +447,7 @@ ENDPROC(__switch_to)
> #endif
>
> .section ".rodata"
> + .align LGREG
> /* Exception vector table */
> ENTRY(excp_vect_table)
> RISCV_PTR do_trap_insn_misaligned
> --
> 2.20.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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