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Message-ID: <20210323203508.GA1251968@robh.at.kernel.org>
Date: Tue, 23 Mar 2021 14:35:08 -0600
From: Rob Herring <robh@...nel.org>
To: Greentime Hu <greentime.hu@...ive.com>
Cc: paul.walmsley@...ive.com, hes@...ive.com, erik.danie@...ive.com,
zong.li@...ive.com, bhelgaas@...gle.com, palmer@...belt.com,
aou@...s.berkeley.edu, mturquette@...libre.com, sboyd@...nel.org,
lorenzo.pieralisi@....com, p.zabel@...gutronix.de,
alex.dewar90@...il.com, khilman@...libre.com,
hayashi.kunihiko@...ionext.com, vidyas@...dia.com,
jh80.chung@...sung.com, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
helgaas@...nel.org
Subject: Re: [PATCH v2 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host
controller
On Thu, Mar 18, 2021 at 02:08:11PM +0800, Greentime Hu wrote:
> Add PCIe host controller DT bindings of SiFive FU740.
>
> Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
> ---
> .../bindings/pci/sifive,fu740-pcie.yaml | 119 ++++++++++++++++++
> 1 file changed, 119 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
> new file mode 100644
> index 000000000000..c25a91b18cd7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
> @@ -0,0 +1,119 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SiFive fu740 PCIe host controller
> +
> +description:
> + SiFive fu740 PCIe host controller is based on the Synopsys DesignWare
> + PCI core. It shares common features with the PCIe DesignWare core and
> + inherits common properties defined in
> + Documentation/devicetree/bindings/pci/designware-pcie.txt.
> +
> +maintainers:
> + - Paul Walmsley <paul.walmsley@...ive.com>
> + - Greentime Hu <greentime.hu@...ive.com>
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> + compatible:
> + const: sifive,fu740-pcie
> +
> + reg:
> + maxItems: 4
What's the 4th item because there's only 3 names:
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: config
> + - const: mgmt
> +
> + device_type:
> + const: pci
Already in pci-bus.yaml
> +
> + dma-coherent:
> + description: Indicates that the PCIe IP block can ensure the coherency
> +
> + bus-range:
> + description: Range of bus numbers associated with this controller.
Already in pci-bus.yaml
> +
> + num-lanes: true
Need to define possible values if not all of 1,2,4,8,16.
> +
> + msi-parent: true
> +
> + interrupt-names:
> + items:
> + - const: msi
> + - const: inta
> + - const: intb
> + - const: intc
> + - const: intd
> +
> + resets:
> + description: A phandle to the PCIe power up reset line
> +
> + pwren-gpios:
> + description: Should specify the GPIO for controlling the PCI bus device power on
maxItems: 1
> +
> + perstn-gpios:
> + description: Should specify the GPIO for controlling the PCI bus device reset
The DWC binding and pci.txt already define 'reset-gpios' for this
purpose.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - device_type
pci-bus.yaml already requires this.
> + - dma-coherent
> + - bus-range
This generally doesn't need to be required unless the h/w can't support
0-0xff.
> + - ranges
pci-bus.yaml already requires this.
> + - num-lanes
> + - interrupts
> + - interrupt-names
> + - interrupt-parent
> + - interrupt-map-mask
> + - interrupt-map
> + - clock-names
> + - clocks
> + - resets
> + - pwren-gpios
> + - perstn-gpios
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pcie@...000000 {
> + #address-cells = <3>;
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + compatible = "sifive,fu740-pcie";
> + reg = <0xe 0x00000000 0x1 0x0
Humm, 4GB for DBI space? The DWC controller doesn't have that much
space, and the kernel will map *all* of that. That's not an
insignificant amount of memory just for page tables.
> + 0xd 0xf0000000 0x0 0x10000000
> + 0x0 0x100d0000 0x0 0x1000>;
<> around each reg entry.
> + reg-names = "dbi", "config", "mgmt";
> + device_type = "pci";
> + dma-coherent;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 /* I/O */
> + 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 /* mem */
> + 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 /* mem */
> + 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
<> around each ranges entry.
> + num-lanes = <0x8>;
> + interrupts = <56 57 58 59 60 61 62 63 64>;
And here.
> + interrupt-names = "msi", "inta", "intb", "intc", "intd";
> + interrupt-parent = <&plic0>;
> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
> + <0x0 0x0 0x0 0x2 &plic0 58>,
> + <0x0 0x0 0x0 0x3 &plic0 59>,
> + <0x0 0x0 0x0 0x4 &plic0 60>;
> + clock-names = "pcie_aux";
> + clocks = <&prci PRCI_CLK_PCIE_AUX>;
> + resets = <&prci 4>;
> + pwren-gpios = <&gpio 5 0>;
> + perstn-gpios = <&gpio 8 0>;
> + };
> --
> 2.30.2
>
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