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Message-ID: <19f83ca486e4d7bc7dadf2470356c888ba64e583.camel@nxp.com>
Date: Tue, 23 Mar 2021 11:42:40 +0800
From: Liu Ying <victor.liu@....com>
To: Marcel Ziswiler <marcel.ziswiler@...adex.com>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-media@...r.kernel.org" <linux-media@...r.kernel.org>
Cc: "narmstrong@...libre.com" <narmstrong@...libre.com>,
"linux-imx@....com" <linux-imx@....com>,
"robert.foss@...aro.org" <robert.foss@...aro.org>,
"Laurent.pinchart@...asonboard.com"
<Laurent.pinchart@...asonboard.com>,
"mchehab@...nel.org" <mchehab@...nel.org>,
"daniel@...ll.ch" <daniel@...ll.ch>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"vkoul@...nel.org" <vkoul@...nel.org>,
"kernel@...gutronix.de" <kernel@...gutronix.de>,
"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
"a.hajda@...sung.com" <a.hajda@...sung.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"jonas@...boo.se" <jonas@...boo.se>,
"kishon@...com" <kishon@...com>,
"airlied@...ux.ie" <airlied@...ux.ie>,
"festevam@...il.com" <festevam@...il.com>,
"lee.jones@...aro.org" <lee.jones@...aro.org>,
"jernej.skrabec@...l.net" <jernej.skrabec@...l.net>
Subject: Re: [PATCH v6 05/14] dt-bindings: display: bridge: Add i.MX8qm/qxp
display pixel link binding
Hi Marcel,
On Tue, 2021-03-23 at 00:38 +0000, Marcel Ziswiler wrote:
> On Wed, 2021-03-17 at 11:42 +0800, Liu Ying wrote:
> > This patch adds bindings for i.MX8qm/qxp display pixel link.
> >
> > Reviewed-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@...lic.gmane.org>
> > Signed-off-by: Liu Ying <victor.liu-3arQi8VN3Tc@...lic.gmane.org>
> > ---
> > v5->v6:
> > * No change.
> >
> > v4->v5:
> > * No change.
> >
> > v3->v4:
> > * No change.
> >
> > v2->v3:
> > * Add Rob's R-b tag.
> >
> > v1->v2:
> > * Use graph schema. (Laurent)
> > * Require all four pixel link output ports. (Laurent)
> > * Mention pixel link is accessed via SCU firmware. (Rob)
> >
> > .../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +++++++++++++++++++++
> > 1 file changed, 106 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> > new file mode 100644
> > index 00000000..3af67cc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> > @@ -0,0 +1,106 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fbridge%2Ffsl%2Cimx8qxp-pixel-link.yaml%23&data=04%7C01%7Cvictor.liu%40nxp.com%7C281077e1c1324aa89ad008d8ed93f1f0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637520566973165920%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=2NDRsaWJ6YGFg%2FWAjT1Yf9Y0OaRDSHG0fWghi9UKNRA%3D&reserved=0
> > +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cvictor.liu%40nxp.com%7C281077e1c1324aa89ad008d8ed93f1f0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637520566973165920%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=ogBn2bQmj1YwDqg0KDMXZ%2FwL0VkdOA14n5ayBioMcos%3D&reserved=0
> > +
> > +title: Freescale i.MX8qm/qxp Display Pixel Link
> > +
> > +maintainers:
> > + - Liu Ying <victor.liu-3arQi8VN3Tc@...lic.gmane.org>
> > +
> > +description: |
> > + The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
> > + asynchronous linkage between pixel sources(display controller or
> > + camera module) and pixel consumers(imaging or displays).
> > + It consists of two distinct functions, a pixel transfer function and a
> > + control interface. Multiple pixel channels can exist per one control channel.
> > + This binding documentation is only for pixel links whose pixel sources are
> > + display controllers.
> > +
> > + The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
> > + firmware.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - fsl,imx8qm-dc-pixel-link
> > + - fsl,imx8qxp-dc-pixel-link
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port@0:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: The pixel link input port node from upstream video source.
> > +
> > + patternProperties:
> > + "^port@[1-4]$":
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: The pixel link output port node to downstream bridge.
> > +
> > + required:
> > + - port@0
> > + - port@1
> > + - port@2
> > + - port@3
> > + - port@4
> > +
> > +required:
> > + - compatible
> > + - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + dc0-pixel-link0 {
> > + compatible = "fsl,imx8qxp-dc-pixel-link";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* from dc0 pixel combiner channel0 */
> > + port@0 {
> > + reg = <0>;
> > +
> > + dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
> > + remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
> > + };
> > + };
> > +
> > + /* to PXL2DPIs in MIPI/LVDS combo subsystems */
> > + port@1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <1>;
> > +
> > + dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
> > + };
> > +
> > + dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
>
> Those also seem absent from other examples.
Patch 8/14 adds dt-binding for PXL2DPI. An example for the PXL2DPI
instance in 'mipi_lvds_0' subsystem is provided there. It doesn't make
too much sense to provide examples for both 'mipi_lvds_0' subsystem
and 'mipi_lvds_1' subsystem, IMHO. I think it's common that people
usually provide an example for one hardware instance.
Regards,
Liu Ying
>
> > + };
> > + };
> > +
> > + /* unused */
> > + port@2 {
> > + reg = <2>;
> > + };
> > +
> > + /* unused */
> > + port@3 {
> > + reg = <3>;
> > + };
> > +
> > + /* to imaging subsystem */
> > + port@4 {
> > + reg = <4>;
> > + };
> > + };
> > + };
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