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Message-ID: <dd102327-e031-9eb1-3ba5-e681f305a495@intel.com>
Date: Thu, 25 Mar 2021 07:34:14 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Brijesh Singh <brijesh.singh@....com>,
linux-kernel@...r.kernel.org, x86@...nel.org, kvm@...r.kernel.org,
linux-crypto@...r.kernel.org
Cc: ak@...ux.intel.com, herbert@...dor.apana.org.au,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Joerg Roedel <jroedel@...e.de>,
"H. Peter Anvin" <hpa@...or.com>, Tony Luck <tony.luck@...el.com>,
"Peter Zijlstra (Intel)" <peterz@...radead.org>,
Paolo Bonzini <pbonzini@...hat.com>,
Tom Lendacky <thomas.lendacky@....com>,
David Rientjes <rientjes@...gle.com>,
Sean Christopherson <seanjc@...gle.com>
Subject: Re: [RFC Part2 PATCH 05/30] x86: define RMP violation #PF error code
On 3/25/21 7:32 AM, Brijesh Singh wrote:
>>> enum x86_pf_error_code {
>>> X86_PF_PROT = 1 << 0,
>>> @@ -21,6 +22,7 @@ enum x86_pf_error_code {
>>> X86_PF_INSTR = 1 << 4,
>>> X86_PF_PK = 1 << 5,
>>> X86_PF_SGX = 1 << 15,
>>> + X86_PF_RMP = 1ull << 31,
>>> };
...
>> Could we at least start declaring these with BIT()?
>
> Sure, I can bit the BIT() macro to define the bits. Do you want me to
> update all of the fault codes to use BIT() or just the one I am adding
> in this patch ?
Please update all of them for consistency.
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