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Message-ID: <CADnq5_Nwwg2wEUO-Y8q96i_Xj0fHUGYguytesFq3Fooqqk4mUA@mail.gmail.com>
Date: Thu, 25 Mar 2021 13:03:01 -0400
From: Alex Deucher <alexdeucher@...il.com>
To: Randy Dunlap <rdunlap@...radead.org>
Cc: Bhaskar Chowdhury <unixbhaskar@...il.com>,
"Deucher, Alexander" <alexander.deucher@....com>,
Christian Koenig <christian.koenig@....com>,
Dave Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
amd-gfx list <amd-gfx@...ts.freedesktop.org>,
Maling list - DRI developers
<dri-devel@...ts.freedesktop.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V2] drm/radeon/r600_cs: Few typo fixes
Applied. Thanks!
Alex
On Wed, Mar 24, 2021 at 7:46 PM Randy Dunlap <rdunlap@...radead.org> wrote:
>
> On 3/24/21 4:29 PM, Bhaskar Chowdhury wrote:
> > s/miror/mirror/
> > s/needind/needing/
> > s/informations/information/
> >
> > Signed-off-by: Bhaskar Chowdhury <unixbhaskar@...il.com>
>
> Acked-by: Randy Dunlap <rdunlap@...radead.org>
>
> Thanks.
>
> > ---
> > Changes from V1:
> > Randy's finding incorporated ,i.e in one place,informations->information
> > Adjusted the subject line accordingly
> >
> > drivers/gpu/drm/radeon/r600_cs.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
> > index 34b7c6f16479..8be4799a98ef 100644
> > --- a/drivers/gpu/drm/radeon/r600_cs.c
> > +++ b/drivers/gpu/drm/radeon/r600_cs.c
> > @@ -38,7 +38,7 @@ extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes,
> >
> >
> > struct r600_cs_track {
> > - /* configuration we miror so that we use same code btw kms/ums */
> > + /* configuration we mirror so that we use same code btw kms/ums */
> > u32 group_size;
> > u32 nbanks;
> > u32 npipes;
> > @@ -963,7 +963,7 @@ static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
> > *
> > * This function will test against r600_reg_safe_bm and return 0
> > * if register is safe. If register is not flag as safe this function
> > - * will test it against a list of register needind special handling.
> > + * will test it against a list of register needing special handling.
> > */
> > static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
> > {
> > @@ -2336,7 +2336,7 @@ int r600_cs_parse(struct radeon_cs_parser *p)
> > /**
> > * r600_dma_cs_next_reloc() - parse next reloc
> > * @p: parser structure holding parsing context.
> > - * @cs_reloc: reloc informations
> > + * @cs_reloc: reloc information
> > *
> > * Return the next reloc, do bo validation and compute
> > * GPU offset using the provided start.
> > --
>
>
> --
> ~Randy
>
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