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Message-ID: <25e4c77d-7548-a135-3f94-4f6224de1f91@gmail.com>
Date: Mon, 29 Mar 2021 19:12:10 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: Michael Kao <michael.kao@...iatek.com>, fan.chen@...iatek.com,
Zhang Rui <rui.zhang@...el.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
linux-pm@...r.kernel.org, srv_heupstream@...iatek.com
Cc: Eduardo Valentin <edubezval@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>, hsinyi@...omium.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Matthias Kaehlcke <mka@...omium.org>
Subject: Re: [v7,2/3] arm64: dts: mt8183: Configure CPU cooling
On 16/03/2021 08:01, Michael Kao wrote:
> From: Matthias Kaehlcke <mka@...omium.org>
>
> Add two passive trip points at 68°C and 80°C for the CPU temperature.
>
> Signed-off-by: Matthias Kaehlcke <mka@...omium.org>
> Signed-off-by: Michael Kao <michael.kao@...iatek.com>
> Tested-by: Hsin-Yi Wang <hsinyi@...omium.org>
Applied to v5.12-next/dts64
Thanks.
Matthias
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 56 ++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index d3550af06408..1ad0a1d55d53 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -13,6 +13,7 @@
> #include <dt-bindings/power/mt8183-power.h>
> #include <dt-bindings/reset-controller/mt8183-resets.h>
> #include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/thermal/thermal.h>
> #include "mt8183-pinfunc.h"
>
> / {
> @@ -678,6 +679,61 @@
> polling-delay = <500>;
> thermal-sensors = <&thermal 0>;
> sustainable-power = <5000>;
> +
> + trips {
> + threshold: trip-point@0 {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + target: trip-point@1 {
> + temperature = <80000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit: cpu-crit {
> + temperature = <115000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&target>;
> + cooling-device = <&cpu0
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu1
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu2
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu3
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>;
> + contribution = <3072>;
> + };
> + map1 {
> + trip = <&target>;
> + cooling-device = <&cpu4
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu5
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu6
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu7
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>;
> + contribution = <1024>;
> + };
> + };
> };
>
> /* The tzts1 ~ tzts6 don't need to polling */
>
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