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Message-ID: <985bd950-7bdf-d9b5-0a89-c05a56739c68@ti.com>
Date: Tue, 30 Mar 2021 14:59:16 +0530
From: Kishon Vijay Abraham I <kishon@...com>
To: Rob Herring <robh@...nel.org>
CC: Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Marc Zyngier <maz@...nel.org>, <linux-pci@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
Lokesh Vutla <lokeshvutla@...com>
Subject: Re: [PATCH 1/6] dt-bindings: PCI: ti,am65: Add PCIe host mode
dt-bindings for TI's AM65 SoC
Hi Rob,
On 26/03/21 5:08 am, Rob Herring wrote:
> On Thu, Mar 25, 2021 at 02:30:21PM +0530, Kishon Vijay Abraham I wrote:
>> Add PCIe host mode dt-bindings for TI's AM65 SoC.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
>> ---
>> .../bindings/pci/ti,am65-pci-host.yaml | 111 ++++++++++++++++++
>> 1 file changed, 111 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
>> new file mode 100644
>> index 000000000000..b77e492886fa
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
>> @@ -0,0 +1,111 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: TI AM65 PCI Host
>> +
>> +maintainers:
>> + - Kishon Vijay Abraham I <kishon@...com>
>> +
>> +allOf:
>> + - $ref: /schemas/pci/pci-bus.yaml#
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - ti,am654-pcie-rc
>> +
>> + reg:
>> + maxItems: 4
>> +
>> + reg-names:
>> + items:
>> + - const: app
>> + - const: dbics
>
> Please use 'dbi' like everyone else if this isn't shared with the other
> TI DW PCI bindings.
I'm just converting existing binding in pci-keystone.txt to yaml.
Documentation/devicetree/bindings/pci/pci-keystone.txt
Device tree for AM65 is also already in the upstream kernel.
I can try to remove the am65 specific part from pci-keystone.txt
>
>> + - const: config
>> + - const: atu
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + ti,syscon-pcie-id:
>> + description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> +
>> + ti,syscon-pcie-mode:
>> + description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> +
>> + msi-map: true
>> +
>> + dma-coherent: true
>> +
>> +patternProperties:
>> + "interrupt-controller":
>
> Don't need quotes.
sure, will fix it.
>
>> + type: object
>> + description: interrupt controller to handle legacy interrupts.
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - max-link-speed
>> + - num-lanes
>> + - power-domains
>> + - ti,syscon-pcie-id
>> + - ti,syscon-pcie-mode
>> + - msi-map
>> + - ranges
>> + - reset-gpios
>> + - phys
>> + - phy-names
>> + - dma-coherent
>
> 'interrupt-controller' node is optional?
yeah, upstream DT doesn't have interrupt-controller. It's added as part
of this series.
Thanks
Kishon
>
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/soc/ti,sci_pm_domain.h>
>> + #include <dt-bindings/gpio/gpio.h>
>> +
>> + bus {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + pcie0_rc: pcie@...0000 {
>> + compatible = "ti,am654-pcie-rc";
>> + reg = <0x0 0x5500000 0x0 0x1000>,
>> + <0x0 0x5501000 0x0 0x1000>,
>> + <0x0 0x10000000 0x0 0x2000>,
>> + <0x0 0x5506000 0x0 0x1000>;
>> + reg-names = "app", "dbics", "config", "atu";
>> + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
>> + <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
>> + ti,syscon-pcie-id = <&pcie_devid>;
>> + ti,syscon-pcie-mode = <&pcie0_mode>;
>> + bus-range = <0x0 0xff>;
>> + num-viewport = <16>;
>> + max-link-speed = <2>;
>> + dma-coherent;
>> + interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
>> + msi-map = <0x0 &gic_its 0x0 0x10000>;
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
>> + <0 0 0 2 &pcie0_intc 0>, /* INT B */
>> + <0 0 0 3 &pcie0_intc 0>, /* INT C */
>> + <0 0 0 4 &pcie0_intc 0>; /* INT D */
>> +
>> + pcie0_intc: interrupt-controller {
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + interrupt-parent = <&gic500>;
>> + interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
>> + };
>> + };
>> --
>> 2.17.1
>>
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