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Message-ID: <af099fda-a7be-8fe5-ed9e-cfcd6f13c09c@linaro.org>
Date: Wed, 31 Mar 2021 16:40:07 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Jordan Crouse <jcrouse@...eaurora.org>,
linux-arm-msm@...r.kernel.org
Cc: Akhil P Oommen <akhilpo@...eaurora.org>,
Daniel Vetter <daniel@...ll.ch>,
David Airlie <airlied@...ux.ie>, Eric Anholt <eric@...olt.net>,
Jonathan Marek <jonathan@...ek.ca>,
Rob Clark <robdclark@...il.com>,
Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>,
Sean Paul <sean@...rly.run>,
Sharat Masetty <smasetty@...eaurora.org>,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] drm/msm: a6xx: Make sure the SQE microcode is safe
Hello,
On 10/02/2021 03:52, Jordan Crouse wrote:
> Most a6xx targets have security issues that were fixed with new versions
> of the microcode(s). Make sure that we are booting with a safe version of
> the microcode for the target and print a message and error if not.
>
> v2: Add more informative error messages and fix typos
>
> Signed-off-by: Jordan Crouse <jcrouse@...eaurora.org>
[skipped]
> + } else {
> + /*
> + * a650 tier targets don't need whereami but still need to be
> + * equal to or newer than 1.95 for other security fixes
> + */
> + if (adreno_is_a650(adreno_gpu)) {
> + if ((buf[0] & 0xfff) >= 0x195) {
> + ret = true;
> + goto out;
> + }
I think this is incorrect. The latest firmware i have here also fails
this check, with the buf[0] = 0x016dd099, so buf[0] & 0xfff = 0x099.
Could you please confirm the versioning?
> +
> + DRM_DEV_ERROR(&gpu->pdev->dev,
> + "a650 SQE ucode is too old. Have version %x need at least %x\n",
> + buf[0] & 0xfff, 0x195);
> + }
> +
> + /*
> + * When a660 is added those targets should return true here
> + * since those have all the critical security fixes built in
> + * from the start
> + */
> + }
> +out:
> msm_gem_put_vaddr(obj);
> + return ret;
> }
>
> static int a6xx_ucode_init(struct msm_gpu *gpu)
> @@ -566,7 +611,13 @@ static int a6xx_ucode_init(struct msm_gpu *gpu)
> }
>
> msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
> - a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo);
> + if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) {
> + msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
> + drm_gem_object_put(a6xx_gpu->sqe_bo);
> +
> + a6xx_gpu->sqe_bo = NULL;
> + return -EPERM;
> + }
> }
>
> gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,
--
With best wishes
Dmitry
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