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Message-ID: <6dfd1108-deaa-8606-01a9-4739e7c2da91@i2se.com>
Date: Fri, 9 Apr 2021 20:28:59 +0200
From: Stefan Wahren <stefan.wahren@...e.com>
To: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>,
Alan Cooper <alcooperx@...il.com>,
Florian Fainelli <f.fainelli@...il.com>,
Scott Branden <sbranden@...adcom.com>
Cc: Nicolas Saenz Julienne <nsaenz@...nel.org>,
"moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
linux-mmc <linux-mmc@...r.kernel.org>,
DTML <devicetree@...r.kernel.org>,
BCM Kernel Feedback <bcm-kernel-feedback-list@...adcom.com>,
linux-rpi-kernel@...ts.infradead.org, phil@...pberrypi.com,
Tim Gover <tim.gover@...pberrypi.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Ulf Hansson <ulf.hansson@...aro.org>,
Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH 4/4] ARM: dts: Fix-up EMMC2 controller's frequency
Hi Nicolas,
Am 09.04.21 um 12:54 schrieb Nicolas Saenz Julienne:
> Hi again,
>
> On Wed, 2021-04-07 at 16:37 -0400, Alan Cooper wrote:
>> Nicolas,
>>
>> I got a better description of the failure and it looks like the bus
>> clock needs to be limited to 300KHz for a 500MHz core clock.
>> What's happening is that an internal reset sequence is needed after a
>> command timeout and the reset signal needs to be asserted for at least
>> 2 ticks of the bus clock. This is done using a 12 bit counter clocked
>> by the core clock. That means a 500MHz core clock produces a 122KHz
>> reset signal which is too fast for 2 ticks of the 200KHz bus clock
>> (100KHz) but is okay for the 300KHz (150Khz) bus clock.
> Is there any value in implementing this in a generic way?
i don't have any idea which callback could manipulate the reset
duration. Limiting the min clk frequency looks like the less invasive
solution to me. Touching the DT isn't recommend.
Best regards
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