linux-kernel - Re: [PATCH 4/4] ARM: dts: Fix-up EMMC2 controller's frequency

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <2dbb9e8c1f1e107712b05e36aa1b244329381425.camel@suse.de>
Date:   Fri, 09 Apr 2021 12:54:26 +0200
From:   Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
To:     Alan Cooper <alcooperx@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Scott Branden <sbranden@...adcom.com>
Cc:     Stefan Wahren <stefan.wahren@...e.com>,
        Nicolas Saenz Julienne <nsaenz@...nel.org>,
        "moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        linux-mmc <linux-mmc@...r.kernel.org>,
        DTML <devicetree@...r.kernel.org>,
        BCM Kernel Feedback <bcm-kernel-feedback-list@...adcom.com>,
        linux-rpi-kernel@...ts.infradead.org,
        Florian Fainelli <f.fainelli@...il.com>, phil@...pberrypi.com,
        Tim Gover <tim.gover@...pberrypi.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH 4/4] ARM: dts: Fix-up EMMC2 controller's frequency

Hi again,

On Wed, 2021-04-07 at 16:37 -0400, Alan Cooper wrote:
> Nicolas,
> 
> I got a better description of the failure and it looks like the bus
> clock needs to be limited to 300KHz for a 500MHz core clock.
> What's happening is that an internal reset sequence is needed after a
> command timeout and the reset signal needs to be asserted for at least
> 2 ticks of the bus clock. This is done using a 12 bit counter clocked
> by the core clock. That means a 500MHz core clock produces a 122KHz
> reset signal which is too fast for 2 ticks of the 200KHz bus clock
> (100KHz) but is okay for the 300KHz (150Khz) bus clock.

Is there any value in implementing this in a generic way? That is, will a SoC
other than BCM2711 ever need this? Otherwise I can simply limit BCM2711's
sdhci-iproc min clk frequency to 300KHz and call it a day.

The alternative is something the likes of:

	min_clk = clk_get_rate(core_bus) >> 11;

But it involves updating the bindings and DT.

Regards,
Nicolas




Download attachment "signature.asc" of type "application/pgp-signature" (489 bytes)