linux-kernel - Re: [PATCH v2 0/7] gpio-rockchip driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAMdYzYrSwLd7zAo840VvQNs48ki1kwS2LdL+N96aVKrmrMRWbw@mail.gmail.com>
Date:   Mon, 12 Apr 2021 11:00:18 -0400
From:   Peter Geis <pgwipeout@...il.com>
To:     Andy Shevchenko <andy.shevchenko@...il.com>
Cc:     Heiko Stübner <heiko@...ech.de>,
        Jianqun Xu <jay.xu@...k-chips.com>,
        Tao Huang <huangtao@...k-chips.com>,
        Kever Yang <kever.yang@...k-chips.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 0/7] gpio-rockchip driver

On Mon, Apr 12, 2021 at 9:34 AM Andy Shevchenko
<andy.shevchenko@...il.com> wrote:
>
> On Mon, Apr 12, 2021 at 4:30 PM Heiko Stübner <heiko@...ech.de> wrote:
> > Am Montag, 12. April 2021, 14:13:37 CEST schrieb Andy Shevchenko:
> > > On Sun, Apr 11, 2021 at 4:35 PM Peter Geis <pgwipeout@...il.com> wrote:
> > > >
> > > > Separate gpio driver from pinctrl driver, and support v2 controller.
> > > >
> > > > Tested on rk3566-quartz64 prototype board.
> > >
> > > Can you give a bit more context?
> > > Usually separation means that hardware is represented by two different
> > > IP blocks that are (almost) independent to each other. Was it the case
> > > on the original platforms? Do you have different pin controller (or
> > > it's absent completely) on some new / old platform?
> >
> > They are separate on all Rockchip SoCs.
> >
> > I.e. the pinconfig (muxing, pulls, etc) is done via some registers inside
> > the "General Register Files" [area for misc registers]
> > and control for the gpio functionality is done in separate blocks
> > for each bank.
> >
> > Lumping that stuff together into one driver, was a design-mistake
> > from younger-me back in 2013 ;-)
>
> Thanks!
>
> To the submitter: Just for the future, please elaborate such things in
> the cover letter.

Apologies, I only rebased the work and reused the original cover letter.
I'll keep that in mind if this sort of situation arises again.

>
> --
> With Best Regards,
> Andy Shevchenko