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Message-ID: <CAHp75VdWES51UPiKayYZ15Mr7pS-Aaz51hKNFmyhbv2JqwPwPA@mail.gmail.com>
Date: Mon, 12 Apr 2021 16:33:48 +0300
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Heiko Stübner <heiko@...ech.de>
Cc: Peter Geis <pgwipeout@...il.com>,
Jianqun Xu <jay.xu@...k-chips.com>,
Tao Huang <huangtao@...k-chips.com>,
Kever Yang <kever.yang@...k-chips.com>,
Linus Walleij <linus.walleij@...aro.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
linux-rockchip@...ts.infradead.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 0/7] gpio-rockchip driver
On Mon, Apr 12, 2021 at 4:30 PM Heiko Stübner <heiko@...ech.de> wrote:
> Am Montag, 12. April 2021, 14:13:37 CEST schrieb Andy Shevchenko:
> > On Sun, Apr 11, 2021 at 4:35 PM Peter Geis <pgwipeout@...il.com> wrote:
> > >
> > > Separate gpio driver from pinctrl driver, and support v2 controller.
> > >
> > > Tested on rk3566-quartz64 prototype board.
> >
> > Can you give a bit more context?
> > Usually separation means that hardware is represented by two different
> > IP blocks that are (almost) independent to each other. Was it the case
> > on the original platforms? Do you have different pin controller (or
> > it's absent completely) on some new / old platform?
>
> They are separate on all Rockchip SoCs.
>
> I.e. the pinconfig (muxing, pulls, etc) is done via some registers inside
> the "General Register Files" [area for misc registers]
> and control for the gpio functionality is done in separate blocks
> for each bank.
>
> Lumping that stuff together into one driver, was a design-mistake
> from younger-me back in 2013 ;-)
Thanks!
To the submitter: Just for the future, please elaborate such things in
the cover letter.
--
With Best Regards,
Andy Shevchenko
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