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Message-ID: <2834595e6552c81441592a57dc41146d46484143.camel@calian.com>
Date:   Fri, 16 Apr 2021 16:05:49 +0000
From:   Robert Hancock <robert.hancock@...ian.com>
To:     "maz@...nel.org" <maz@...nel.org>
CC:     "tglx@...utronix.de" <tglx@...utronix.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "michal.simek@...inx.com" <michal.simek@...inx.com>
Subject: Re: [PATCH] irqchip/xilinx: Expose Kconfig option

On Fri, 2021-04-16 at 14:41 +0100, Marc Zyngier wrote:
> On Fri, 16 Apr 2021 00:32:50 +0100,
> Robert Hancock <robert.hancock@...ian.com> wrote:
> > Previously the XILINX_INTC config option was hidden and only
> > auto-selected on the MicroBlaze platform. However, this IP can also be
> > used on other platforms. Allow this option to be user-enabled.
> > 
> > Signed-off-by: Robert Hancock <robert.hancock@...ian.com>
> 
> I don't think this is a good idea. In general, people have no idea
> which interrupt controller they need to select. So you either end-up
> with a missing interrupt controller, or a bunch you really don't need.
> 
> This is essentially a platform constraint, and this should directly be
> selected by the platform if you have this IP in your system.
> 
> Thanks,
> 
> 	M.

The problem is essentially that at the platform level, we don't know, other
than in the MicroBlaze case where we know it will be used as the platform's
primary interrupt controller. In our case, we are using this IP core on the
ZynqMP platform as a secondary cascaded interrupt controller in the FPGA
portion of the device. But many ZynqMP configurations wouldn't have this device
present, it depends on what the user instantiates in the programmable logic.
Also, this core could just as easily be instantiated in standalone Xilinx FPGAs
which could be connected to many different platforms over a PCIe, AXI, etc.
bus. So I don't think having this as a platform constraint makes sense.

-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com

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