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Message-ID: <mhng-cec1febb-7da2-4d6e-9c38-3b1580b75e19@palmerdabbelt-glaptop>
Date: Thu, 22 Apr 2021 20:32:44 -0700 (PDT)
From: Palmer Dabbelt <palmer@...belt.com>
To: xypron.glpk@....de
CC: robh+dt@...nel.org, Paul Walmsley <paul.walmsley@...ive.com>,
aou@...s.berkeley.edu, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org
Subject: Re: [RFC] dt-bindings: riscv: enum for riscv,isa
On Tue, 06 Apr 2021 12:05:34 PDT (-0700), xypron.glpk@....de wrote:
> In Documentation/devicetree/bindings/riscv/cpus.yaml I find for riscv,isa:
>
> enum:
> - rv64imac
> - rv64imafdc
>
> This implies that 'rv64imafc' or 'rv64imafdqc' would be illegal values
> while these combinations of extensions would be compliant with "The
> RISC-V Instruction Set Manual".
>
> To me it does not make much sense to try to enumerate all permissible
> permutations of RISC-V extensions.
>
> Shouldn't this enum be removed and replaced by examples?
I'm generally OK with that, but I'm not sure how to do it: won't we fail
the scheme checks if we don't have something defined for "riscv,isa"?
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