linux-kernel - Re: [PATCH] fpga: dfl: pci: gracefully handle misconfigured port entries

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YIYVtbgIpiH58y8H@epycbox.lan>
Date:   Sun, 25 Apr 2021 18:21:57 -0700
From:   Moritz Fischer <mdf@...nel.org>
To:     matthew.gerlach@...ux.intel.com
Cc:     Tom Rix <trix@...hat.com>, hao.wu@...el.com,
        linux-fpga@...r.kernel.org, linux-kernel@...r.kernel.org,
        yilun.xu@...el.com, russell.h.weight@...el.com, mdf@...nel.org
Subject: Re: [PATCH] fpga: dfl: pci: gracefully handle misconfigured port
 entries

On Tue, Apr 20, 2021 at 12:19:42PM -0700, matthew.gerlach@...ux.intel.com wrote:
> 
> 
> On Tue, 20 Apr 2021, Tom Rix wrote:
> 
> > 
> > On 4/20/21 10:27 AM, matthew.gerlach@...ux.intel.com wrote:
> > > From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
> > > 
> > > Gracefully ignore misconfigured port entries encountered in
> > > incorrect FPGA images.
> > > 
> > > Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
> > > ---
> > >   drivers/fpga/dfl-pci.c | 16 +++++++++++++++-
> > >   1 file changed, 15 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> > > index b44523e..660d3b6 100644
> > > --- a/drivers/fpga/dfl-pci.c
> > > +++ b/drivers/fpga/dfl-pci.c
> > > @@ -212,6 +212,7 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
> > Does something similar need to be added to find_dfls_by_vsec ?
> > >   	int port_num, bar, i, ret = 0;
> > >   	resource_size_t start, len;
> > >   	void __iomem *base;
> > > +	int bars = 0;
> > >   	u32 offset;
> > >   	u64 v;
> > >   @@ -228,6 +229,7 @@ static int find_dfls_by_default(struct pci_dev
> > > *pcidev,
> > >   	if (dfl_feature_is_fme(base)) {
> > >   		start = pci_resource_start(pcidev, 0);
> > >   		len = pci_resource_len(pcidev, 0);
> > > +		bars |= BIT(0);
> > >     		dfl_fpga_enum_info_add_dfl(info, start, len);
> > >   @@ -253,9 +255,21 @@ static int find_dfls_by_default(struct
> > > pci_dev *pcidev,
> > >   			 */
> > >   			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
> > >   			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
> > > +			if (bars & BIT(bar)) {
> > > +				dev_warn(&pcidev->dev, "skipping bad port BAR %d\n", bar);
> > > +				continue;
> > > +			}
> > > +
> > >   			start = pci_resource_start(pcidev, bar) + offset;
> > > -			len = pci_resource_len(pcidev, bar) - offset;
> > > +			len = pci_resource_len(pcidev, bar);
> > > +			if (offset >= len) {
> > > +				dev_warn(&pcidev->dev, "bad port offset %u >= %pa\n",
> > > +					 offset, &len);
Do you want pa or px here?

> > 
> > why %pa,&len for instead of %u,len ?
> > 
> > Tom
> 
> Hi Tom,
> 
> The variable len is of type resource_size_t, and I am following what it says
> to do in Documentation/core-api/printk-formats.rst:
> 
> Physical address types phys_addr_t
> ----------------------------------
> 
> ::
> 
>         %pa[p]  0x01234567 or 0x0123456789abcdef
> 
> For printing a phys_addr_t type (and its derivatives, such as
> resource_size_t) which can vary based on build options, regardless of the
> width of the CPU data path.
> 
> Passed by reference.
> 
> Matthew
> > 
> > > +				continue;
> > > +			}
> > >   +			len -= offset;
> > > +			bars |= BIT(bar);
> > >   			dfl_fpga_enum_info_add_dfl(info, start, len);
> > >   		}
> > >   	} else if (dfl_feature_is_port(base)) {
> > 
> > 

- Moritz