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Message-Id: <20210507101926.25631-1-peng.fan@oss.nxp.com>
Date:   Fri,  7 May 2021 18:19:22 +0800
From:   "Peng Fan (OSS)" <peng.fan@....nxp.com>
To:     jassisinghbrar@...il.com, robh+dt@...nel.org, shawnguo@...nel.org,
        s.hauer@...gutronix.de, o.rempel@...gutronix.de
Cc:     kernel@...gutronix.de, festevam@...il.com, aisheng.dong@....com,
        linux-imx@....com, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Peng Fan <peng.fan@....com>
Subject: [PATCH 0/4] mailbox: imx: add i.MX8ULP MU support

From: Peng Fan <peng.fan@....com>

i.MX8ULP generic MU is a different IP compared with previous i.MX chips.
It has different register layout and bit position, but the register name
and bit definitions are almost same with previous i.MX MU.

So we extend the current imx-mailbox driver to support i.MX8ULP.

Peng Fan (4):
  dt-bindings: mailbox: imx-mu: add i.MX8ULP MU support
  mailbox: imx: replace the xTR/xRR array with single register
  mailbox: imx: add xSR/xCR register array
  mailbox: imx-mailbox: support i.MX8ULP MU

 .../devicetree/bindings/mailbox/fsl,mu.yaml   |   1 +
 drivers/mailbox/imx-mailbox.c                 | 196 +++++++++++-------
 2 files changed, 123 insertions(+), 74 deletions(-)

-- 
2.30.0

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