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Message-ID: <DM6PR04MB6575E3D63982278D2F1CA022FC549@DM6PR04MB6575.namprd04.prod.outlook.com>
Date: Mon, 10 May 2021 09:10:52 +0000
From: Avri Altman <Avri.Altman@....com>
To: Ulf Hansson <ulf.hansson@...aro.org>,
"linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
Adrian Hunter <adrian.hunter@...el.com>
CC: Linus Walleij <linus.walleij@...aro.org>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
Shawn Lin <shawn.lin@...k-chips.com>,
Masami Hiramatsu <masami.hiramatsu@...aro.org>,
"linux-block@...r.kernel.org" <linux-block@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 2/2] mmc: core: Add support for cache ctrl for SD cards
> +static int sd_enable_cache(struct mmc_card *card)
> +{
> + u8 *reg_buf;
> + int err;
> +
> + reg_buf = kzalloc(512, GFP_KERNEL);
> + if (!reg_buf)
> + return -ENOMEM;
> +
> + /*
> + * Set the Cache Enable bit in the performance enhancement register at
> + * 260 bytes offset.
> + */
> + err = sd_write_ext_reg(card, card->ext_perf.fno, card->ext_perf.page,
> + card->ext_perf.offset + 260, 0x1);
> + if (err) {
> + pr_warn("%s: error %d writing Cache Enable bit\n",
> + mmc_hostname(card->host), err);
> + goto out;
> + }
> +
> + err = mmc_poll_for_busy(card,
> SD_WRITE_EXTR_SINGLE_TIMEOUT_MS, false,
> + MMC_BUSY_EXTR_SINGLE);
I think 1sec is for flush cache, but I guess it makes sense to use it here as well.
> + if (!err)
> + card->ext_perf.feature_enabled |= SD_EXT_PERF_CACHE;
Maybe
If (err)
card->ext_perf.feature_enabled &= ~SD_EXT_PERF_CACHE;
and move to out: to catch the sd_write_ext_reg err ?
> +
> +out:
> + kfree(reg_buf);
> + return err;
> +}
> +
> /*
> * Handle the detection and initialisation of a card.
> *
> @@ -1442,6 +1531,13 @@ static int mmc_sd_init_card(struct mmc_host
> *host, u32 ocr,
> goto free_card;
> }
>
> + /* Enable internal SD cache if supported. */
> + if (card->ext_perf.feature_support & SD_EXT_PERF_CACHE) {
> + err = sd_enable_cache(card);
> + if (err)
> + goto free_card;
If cache enablement failed, is it worthwhile to bail out?
Maybe disabling the cache with the appropriate message is enough?
> + }
> +
> if (host->cqe_ops && !host->cqe_enabled) {
> err = host->cqe_ops->cqe_enable(host, card);
> if (!err) {
> @@ -1694,6 +1790,8 @@ static const struct mmc_bus_ops mmc_sd_ops = {
> .alive = mmc_sd_alive,
> .shutdown = mmc_sd_suspend,
> .hw_reset = mmc_sd_hw_reset,
> + .cache_enabled = sd_cache_enabled,
> + .flush_cache = sd_flush_cache,
> };
I would expect 2 more patches in this series:
- flush cache on power down
- cache disablement events?
Thanks,
Avri
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