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Message-Id: <20210518234309.29014-2-ansuelsmth@gmail.com>
Date:   Wed, 19 May 2021 01:43:07 +0200
From:   Ansuel Smith <ansuelsmth@...il.com>
To:     Thara Gopinath <thara.gopinath@...aro.org>
Cc:     Robert Marko <robimarko@...il.com>,
        Ansuel Smith <ansuelsmth@...il.com>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Amit Kucheria <amitk@...nel.org>,
        Zhang Rui <rui.zhang@...el.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH 3/3] drivers: thermal: tsens: check if crit_int is supported in read_irq_state

From: Robert Marko <robimarko@...il.com>

Check if crit_int is supported by the current tsens feat and read crit
field only if needed or the kernel panic for reading unreadable memory.

Signed-off-by: Robert Marko <robimarko@...il.com>
Signed-off-by: Ansuel Smith <ansuelsmth@...il.com>
---
 drivers/thermal/qcom/tsens.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
index 38afde1a599f..27777a05f755 100644
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -325,16 +325,22 @@ static int tsens_read_irq_state(struct tsens_priv *priv, u32 hw_id,
 		ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask);
 		if (ret)
 			return ret;
-		ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id],
-					&d->crit_irq_clear);
-		if (ret)
-			return ret;
-		ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id],
-					&d->crit_irq_mask);
-		if (ret)
-			return ret;
+		if (priv->feat->crit_int) {
+			ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id],
+						&d->crit_irq_clear);
+			if (ret)
+				return ret;
+			ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id],
+						&d->crit_irq_mask);
+			if (ret)
+				return ret;
 
-		d->crit_thresh = tsens_hw_to_mC(s, CRIT_THRESH_0 + hw_id);
+			d->crit_thresh = tsens_hw_to_mC(s, CRIT_THRESH_0 + hw_id);
+		} else {
+			d->crit_irq_clear = 0;
+			d->crit_irq_mask = 0;
+			d->crit_thresh = 0;
+		}
 	} else {
 		/* No mask register on older TSENS */
 		d->up_irq_mask = 0;
-- 
2.30.2

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