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Message-ID: <20210521171930.GE2484@yoga>
Date: Fri, 21 May 2021 12:19:30 -0500
From: Bjorn Andersson <bjorn.andersson@...aro.org>
To: Krishna Manikandan <mkrishn@...eaurora.org>
Cc: dri-devel@...ts.freedesktop.org, linux-arm-msm@...r.kernel.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, kalyan_t@...eaurora.org,
tanmay@...eaurora.org, abhinavk@...eaurora.org,
robdclark@...il.com, swboyd@...omium.org, vinod.koul@...aro.org,
dianders@...omium.org, khsieh@...eaurora.org, robh+dt@...nel.org,
sean@...rly.run, robh@...nel.org,
Chandan Uddaraju <chandanu@...eaurora.org>,
Vara Reddy <varar@...eaurora.org>
Subject: Re: [PATCH v17 4/4] dt-bindings: msm/dp: Add bindings of MSM
DisplayPort controller
On Fri 21 May 05:27 CDT 2021, Krishna Manikandan wrote:
> Add bindings for Snapdragon DisplayPort controller driver.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org>
Regards,
Bjorn
> Signed-off-by: Chandan Uddaraju <chandanu@...eaurora.org>
> Signed-off-by: Vara Reddy <varar@...eaurora.org>
> Signed-off-by: Tanmay Shah <tanmay@...eaurora.org>
> Signed-off-by: Kuogee Hsieh <khsieh@...eaurora.org>
> Signed-off-by: Krishna Manikandan <mkrishn@...eaurora.org>
>
> Changes in V2:
> -Provide details about sel-gpio
>
> Changes in V4:
> -Provide details about max dp lanes
> -Change the commit text
>
> Changes in V5:
> -moved dp.txt to yaml file
>
> Changes in v6:
> - Squash all AUX LUT properties into one pattern Property
> - Make aux-cfg[0-9]-settings properties optional
> - Remove PLL/PHY bindings from DP controller dts
> - Add DP clocks description
> - Remove _clk suffix from clock names
> - Rename pixel clock to stream_pixel
> - Remove redundant bindings (GPIO, PHY, HDCP clock, etc..)
> - Fix indentation
> - Add Display Port as interface of DPU in DPU bindings
> and add port mapping accordingly.
>
> Chages in v7:
> - Add dp-controller.yaml file common between multiple SOC
> - Rename dp-sc7180.yaml to dp-controller-sc7180.yaml
> - change compatible string and add SOC name to it.
> - Remove Root clock generator for pixel clock
> - Add assigned-clocks and assigned-clock-parents bindings
> - Remove redundant properties, descriptions and blank lines
> - Add DP port in DPU bindings
> - Update depends-on tag in commit message and rebase change accordingly
>
> Changes in v8:
> - Add MDSS AHB clock in bindings
>
> Changes in v9:
> - Remove redundant reg-name property
> - Change assigned-clocks and assigned-clocks-parents counts to 2
> - Use IRQ flags in example dts
>
> Changes in v10:
> - Change title of this patch as it does not contain PLL bindings anymore
> - Remove redundant properties
> - Remove use of IRQ flag
> - Fix ports property
>
> Changes in v11:
> - add ports required of both #address-cells and #size-cells
> - add required operating-points-v2
> - add required #sound-dai-cells
> - add required power-domains
> - update maintainer list
>
> Changes in v12:
> - remove soc node from examples (Stephen Boyd)
> - split dpu-sc7180.yaml changes to separate patch (Stephen Boyd)
>
> Changes in v13:
> - add assigned-clocks
> - add assigned-clock-parents
>
> Changes in v14:
> - add reference for ports (Rob Herring)
>
> Changes in v15:
> - drop common properties from ports (Rob Herring)
> ---
> .../bindings/display/msm/dp-controller.yaml | 146 +++++++++++++++++++++
> 1 file changed, 146 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> new file mode 100644
> index 0000000..64d8d9e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> @@ -0,0 +1,146 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MSM Display Port Controller
> +
> +maintainers:
> + - Kuogee Hsieh <khsieh@...eaurora.org>
> +
> +description: |
> + Device tree bindings for DisplayPort host controller for MSM targets
> + that are compatible with VESA DisplayPort interface specification.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sc7180-dp
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: AHB clock to enable register access
> + - description: Display Port AUX clock
> + - description: Display Port Link clock
> + - description: Link interface clock between DP and PHY
> + - description: Display Port Pixel clock
> +
> + clock-names:
> + items:
> + - const: core_iface
> + - const: core_aux
> + - const: ctrl_link
> + - const: ctrl_link_iface
> + - const: stream_pixel
> +
> + assigned-clocks:
> + items:
> + - description: link clock source
> + - description: pixel clock source
> +
> + assigned-clock-parents:
> + items:
> + - description: phy 0 parent
> + - description: phy 1 parent
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + items:
> + - const: dp
> +
> + operating-points-v2:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + "#sound-dai-cells":
> + const: 0
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Input endpoint of the controller
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Output endpoint of the controller
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - phys
> + - phy-names
> + - "#sound-dai-cells"
> + - power-domains
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
> + #include <dt-bindings/power/qcom-aoss-qmp.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + displayport-controller@...0000 {
> + compatible = "qcom,sc7180-dp";
> + reg = <0xae90000 0x1400>;
> + interrupt-parent = <&mdss>;
> + interrupts = <12>;
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> + clock-names = "core_iface", "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> +
> + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
> +
> + phys = <&dp_phy>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + power-domains = <&rpmhpd SC7180_CX>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + endpoint {
> + remote-endpoint = <&dpu_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + endpoint {
> + remote-endpoint = <&typec>;
> + };
> + };
> + };
> + };
> +...
> --
> 2.7.4
>
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