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Message-ID: <2348352.12aM7klthN@jernej-laptop>
Date: Mon, 24 May 2021 14:51:47 +0200
From: Jernej Škrabec <jernej.skrabec@...il.com>
To: Andre Przywara <andre.przywara@....com>,
Maxime Ripard <maxime@...no.tech>
Cc: Chen-Yu Tsai <wens@...e.org>, Rob Herring <robh@...nel.org>,
Icenowy Zheng <icenowy@...c.io>,
Samuel Holland <samuel@...lland.org>,
Ondrej Jirman <megous@...ous.com>,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...glegroups.com,
linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org,
Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>, linux-phy@...ts.infradead.org,
linux-usb@...r.kernel.org
Subject: Re: [PATCH v6 12/17] phy: sun4i-usb: Introduce port2 SIDDQ quirk
Dne ponedeljek, 24. maj 2021 ob 13:59:46 CEST je Maxime Ripard napisal(a):
> Hi
>
> On Wed, May 19, 2021 at 11:41:47AM +0100, Andre Przywara wrote:
> > At least the Allwinner H616 SoC requires a weird quirk to make most
> > USB PHYs work: Only port2 works out of the box, but all other ports
> > need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
> > RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
> > the PMU PHY control register needs to be cleared. For this register to
> > be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....
> >
> > Instead of disguising this as some generic feature, do exactly that
> > in our PHY init:
> > If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
> > this one special clock, and clear the SIDDQ bit. We can pull in the
> > other required clocks via the DT.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@....com>
>
> What is this SIDDQ bit doing exactly?
If this is similar to Rockchip USB PHY, then this bit takes care for powering
up/down analog parts of USB PHY:
https://elixir.bootlin.com/linux/latest/source/drivers/phy/rockchip/phy-rockchip-usb.c#L83
Best regards,
Jernej
>
> I guess we could also expose this using a power-domain if it's relevant?
>
> Maxime
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