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Message-Id: <162246707691.166381.10603183245488189380.b4-ty@nvidia.com>
Date: Mon, 31 May 2021 15:20:26 +0200
From: Thierry Reding <thierry.reding@...il.com>
To: Peter De Schrijver <pdeschrijver@...dia.com>,
Thierry Reding <thierry.reding@...il.com>,
Michael Turquette <mturquette@...libre.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Stephen Boyd <sboyd@...nel.org>,
Dmitry Osipenko <digetx@...il.com>,
Michał Mirosław <mirq-linux@...e.qmqm.pl>,
Prashant Gaikwad <pgaikwad@...dia.com>
Cc: linux-tegra@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: (subset) [PATCH v8 0/9] Couple improvements for Tegra clk driver
From: Thierry Reding <treding@...dia.com>
On Sun, 16 May 2021 19:30:32 +0300, Dmitry Osipenko wrote:
> This series fixes couple minor standalone problems of the Tegra clk
> driver and adds new features.
>
> Changelog:
>
> v8: - Replaced division with a shift, which was suggested by Michał Mirosław
> in a comment to "Handle thermal DIV2 CPU frequency throttling" v7 patch.
> Cortex A9 CPUs don't have hardware divider and shifting is a minor
> improvement here, nevertheless it's good to have it.
>
> [...]
Applied, thanks!
[1/9] clk: tegra30: Use 300MHz for video decoder by default
(no commit info)
[2/9] clk: tegra: Fix refcounting of gate clocks
(no commit info)
[3/9] clk: tegra: Ensure that PLLU configuration is applied properly
(no commit info)
[4/9] clk: tegra: Halve SCLK rate on Tegra20
(no commit info)
[5/9] clk: tegra: Don't allow zero clock rate for PLLs
(no commit info)
[6/9] clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
(no commit info)
[7/9] clk: tegra: Mark external clocks as not having reset control
(no commit info)
[8/9] clk: tegra: Don't deassert reset on enabling clocks
(no commit info)
Best regards,
--
Thierry Reding <treding@...dia.com>
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