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Message-ID: <f875025538713a005b1c18f8eb5c24c0@walle.cc>
Date: Tue, 01 Jun 2021 14:47:15 +0200
From: Michael Walle <michael@...le.cc>
To: Pratyush Yadav <p.yadav@...com>
Cc: Tudor Ambarus <tudor.ambarus@...rochip.com>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>,
Vignesh Raghavendra <vigneshr@...com>,
Mark Brown <broonie@...nel.org>, linux-mtd@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-spi@...r.kernel.org
Subject: Re: [PATCH v2 2/6] mtd: spi-nor: spansion: write 2 bytes when
disabling Octal DTR mode
Am 2021-05-31 20:17, schrieb Pratyush Yadav:
> The Octal DTR configuration is stored in the CFR5V register. This
> register is 1 byte wide. But 1 byte long transactions are not allowed
> in
> 8D-8D-8D mode. Since the next byte address does not contain any
> register, it is safe to write any value to it. Write a 0 to it.
>
> Signed-off-by: Pratyush Yadav <p.yadav@...com>
> ---
Can't say much, because there is no public datasheet, is there?
But looks sane. Same for patch 3/6.
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