linux-kernel - [PATCH 3/8] ARM: dts: wpcm450: Add global control registers (GCR) node

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Message-Id: <20210602120329.2444672-4-j.neuschaefer@gmx.net>
Date:   Wed,  2 Jun 2021 14:03:24 +0200
From:   Jonathan Neuschäfer <j.neuschaefer@....net>
To:     linux-gpio@...r.kernel.org, devicetree@...r.kernel.org
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        Rob Herring <robh+dt@...nel.org>, openbmc@...ts.ozlabs.org,
        Tomer Maimon <tmaimon77@...il.com>,
        Joel Stanley <joel@....id.au>, linux-kernel@...r.kernel.org,
        Jonathan Neuschäfer <j.neuschaefer@....net>
Subject: [PATCH 3/8] ARM: dts: wpcm450: Add global control registers (GCR) node

The Global Control Registers (GCR) are a block of registers in Nuvoton
SoCs that expose misc functionality such as chip model and version
information or pinmux settings.

This patch adds a GCR node to nuvoton-wpcm450.dtsi in preparation for
enabling pinctrl on this SoC.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@....net>
---
 arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
index d7cbeb1874840..8eba4897b41bc 100644
--- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
+++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
@@ -33,6 +33,11 @@ soc {
 		interrupt-parent = <&aic>;
 		ranges;

+		gcr: gcr@...00000 {
+			compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd";
+			reg = <0xb0000000 0x200>;
+		};
+
 		serial0: serial@...00000 {
 			compatible = "nuvoton,wpcm450-uart";
 			reg = <0xb8000000 0x20>;
--
2.30.2