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Date:   Thu, 3 Jun 2021 14:05:53 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Steven Lee <steven_lee@...eedtech.com>
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        Bartosz Golaszewski <bgolaszewski@...libre.com>,
        Rob Herring <robh+dt@...nel.org>,
        Joel Stanley <joel@....id.au>,
        Andrew Jeffery <andrew@...id.au>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:ARM/ASPEED MACHINE SUPPORT" 
        <linux-arm-kernel@...ts.infradead.org>,
        "moderated list:ARM/ASPEED MACHINE SUPPORT" 
        <linux-aspeed@...ts.ozlabs.org>,
        open list <linux-kernel@...r.kernel.org>, Hongweiz@....com,
        ryan_chen@...eedtech.com, Billy Tsai <billy_tsai@...eedtech.com>
Subject: Re: [PATCH v3 3/5] gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

On Thu, Jun 3, 2021 at 1:19 PM Steven Lee <steven_lee@...eedtech.com> wrote:
>
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins.
> In the current driver, the maximum number of gpio pins of SoC is hardcoded
> as 80 and the gpio pin count mask for GPIO Configuration register is
> hardcode as GENMASK(9,6). In addition, some functions uses the hardcoded

use

> value to calculate the gpio offset.
> The patch adds ast2600 compatibles and platform data that includes the
> max number of gpio pins supported by ast2600 and gpio pin count mask for
> GPIO Configuration register.
> The patch also modifies some functions to pass aspeed_sgpio struct for
> calculating gpio offset wihtout using the hardcoded value.

without

...

> +#include <linux/of_device.h>

Why?

...

> +#define GPIO_OFFSET(x)        ((x) & 0x1f)

GENMASK()

...

> +       pdata = of_device_get_match_data(&pdev->dev);

device_get_match_data()

I guess you may replace all those of_*() to the corresponding
device_*() or fwnode_*() calls.

-- 
With Best Regards,
Andy Shevchenko

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