linux-kernel - RE: [PATCH 3/4] ASoC: intel: sof_cs42l42: add support for jsl_cs4242

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Message-ID: <DM6PR11MB364231AEC2208EAF5F898B7A97389@DM6PR11MB3642.namprd11.prod.outlook.com>
Date:   Mon, 7 Jun 2021 16:28:20 +0000
From:   "Lu, Brent" <brent.lu@...el.com>
To:     Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>,
        "alsa-devel@...a-project.org" <alsa-devel@...a-project.org>
CC:     Guennadi Liakhovetski <guennadi.liakhovetski@...ux.intel.com>,
        "Rojewski, Cezary" <cezary.rojewski@...el.com>,
        "R, Dharageswari" <dharageswari.r@...el.com>,
        Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
        Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
        Tzung-Bi Shih <tzungbi@...gle.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Jie Yang <yang.jie@...ux.intel.com>,
        Takashi Iwai <tiwai@...e.com>,
        Liam Girdwood <liam.r.girdwood@...ux.intel.com>,
        "Zhi, Yong" <yong.zhi@...el.com>,
        "Mark Brown" <broonie@...nel.org>,
        Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>,
        "M, Naveen" <naveen.m@...el.com>,
        "Wang, Rander" <rander.wang@...el.com>,
        Bard Liao <yung-chuan.liao@...ux.intel.com>,
        Fred Oh <fred.oh@...ux.intel.com>,
        "Gopal, Vamshi Krishna" <vamshi.krishna.gopal@...el.com>,
        "Nujella, Sathyanarayana" <sathyanarayana.nujella@...el.com>
Subject: RE: [PATCH 3/4] ASoC: intel: sof_cs42l42: add support for
 jsl_cs4242_mx98360a

> >>
> >> This also looks like we have two topologies configuring the same DAIs
> >> differently on different platforms.
> >>
> >> Why can't we pick one configuration that would work in all cases?
> >>
> >
> > The comment just say we are reusing rt5685's sof-jsl-rt5682-mx98360a.tplg.
> > This patch does not care about the dai sequence. Maybe I should reword
> > the commit log.
> 
> I was referring to the bclk frequency, one case uses 2.4 and the other
> 3.072MHz.

The 2.4MHz setting isn't ready when we enabled this codec so we selected
3.072MHz. Since we are updating topology for PLL issue soon, we can change
bclk frequency to 2.4MHz as well. How do you think?

Regards,
Brent