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Message-ID: <20210608153203.GA6802@lst.de>
Date:   Tue, 8 Jun 2021 17:32:03 +0200
From:   'Christoph Hellwig' <hch@....de>
To:     David Laight <David.Laight@...LAB.COM>
Cc:     'Christoph Hellwig' <hch@....de>, Guo Ren <guoren@...nel.org>,
        Nick Kossifidis <mick@....forth.gr>,
        Drew Fustini <drew@...gleboard.org>,
        Anup Patel <anup.patel@....com>,
        Palmer Dabbelt <palmerdabbelt@...gle.com>,
        "wefu@...hat.com" <wefu@...hat.com>,
        Wei Wu (吴伟) <lazyparser@...il.com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-arch <linux-arch@...r.kernel.org>,
        "linux-sunxi@...ts.linux.dev" <linux-sunxi@...ts.linux.dev>,
        Guo Ren <guoren@...ux.alibaba.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Benjamin Koch <snowball@...b.de>,
        Matteo Croce <mcroce@...ux.microsoft.com>,
        Wei Fu <tekkamanninja@...il.com>
Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support

On Tue, Jun 08, 2021 at 03:00:17PM +0000, David Laight wrote:
> It is almost impossible to interface to many ethernet chips without
> either coherent or uncached memory for the descriptor rings.
> The status bits on the transmit ring are particularly problematic.
> 
> The receive ring can be done with writeback+invalidate provided you
> fill a cache line at a time.

It is horrible, but it has been done.  Take a look at:

drivers/net/ethernet/i825xx/lasi_82596.c and
drivers/net/ethernet/seeq/sgiseeq.c

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