lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <7a11939f4c7f4494a7d86b8d5f1bb702@AcuMS.aculab.com>
Date:   Tue, 8 Jun 2021 16:11:15 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Christoph Hellwig' <hch@....de>
CC:     Guo Ren <guoren@...nel.org>, Nick Kossifidis <mick@....forth.gr>,
        "Drew Fustini" <drew@...gleboard.org>,
        Anup Patel <anup.patel@....com>,
        "Palmer Dabbelt" <palmerdabbelt@...gle.com>,
        "wefu@...hat.com" <wefu@...hat.com>,
        Wei Wu (吴伟) <lazyparser@...il.com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-arch <linux-arch@...r.kernel.org>,
        "linux-sunxi@...ts.linux.dev" <linux-sunxi@...ts.linux.dev>,
        Guo Ren <guoren@...ux.alibaba.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Benjamin Koch <snowball@...b.de>,
        Matteo Croce <mcroce@...ux.microsoft.com>,
        Wei Fu <tekkamanninja@...il.com>
Subject: RE: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support

From: 'Christoph Hellwig'
> Sent: 08 June 2021 16:32
> 
> On Tue, Jun 08, 2021 at 03:00:17PM +0000, David Laight wrote:
> > It is almost impossible to interface to many ethernet chips without
> > either coherent or uncached memory for the descriptor rings.
> > The status bits on the transmit ring are particularly problematic.
> >
> > The receive ring can be done with writeback+invalidate provided you
> > fill a cache line at a time.
> 
> It is horrible, but it has been done.  Take a look at:
> 
> drivers/net/ethernet/i825xx/lasi_82596.c and
> drivers/net/ethernet/seeq/sgiseeq.c

I guess that each transmit has to be split into enough
fragments that they fill a cache line.
That won't work with some (probably old now) devices that
require the first fragment to be 64 bytes because it won't
back-up the descriptors after a collision.

It's all as horrid as a DSP we have that can't receive ethernet
frames onto a 4n+2 boundary and doesn't support misaligned accesses.

Mind you, Sun's original Sbus ethernet board had to be given
a 4n aligned rx buffer and then a misaligned copy done in kernel
in order to not drop packets!

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ