linux-kernel - RE: [PATCH v2 rdma-next] RDMA/mlx5: Enable Relaxed Ordering by default for kernel ULPs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <25c32f2a147a4dff8b7d6577286d7954@AcuMS.aculab.com>
Date:   Wed, 9 Jun 2021 15:05:52 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Chuck Lever III' <chuck.lever@...cle.com>
CC:     Christoph Hellwig <hch@....de>, Leon Romanovsky <leon@...nel.org>,
        "Doug Ledford" <dledford@...hat.com>,
        Jason Gunthorpe <jgg@...dia.com>,
        Avihai Horon <avihaih@...dia.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
        Bart Van Assche <bvanassche@....org>,
        "Tom Talpey" <tom@...pey.com>,
        Santosh Shilimkar <santosh.shilimkar@...cle.com>,
        Keith Busch <kbusch@...nel.org>,
        Honggang LI <honli@...hat.com>,
        Max Gurtovoy <mgurtovoy@...dia.com>
Subject: RE: [PATCH v2 rdma-next] RDMA/mlx5: Enable Relaxed Ordering by
 default for kernel ULPs

From: Chuck Lever III
> Sent: 09 June 2021 15:37
> 
> Hi David-
> 
> > On Jun 9, 2021, at 10:10 AM, David Laight <David.Laight@...LAB.COM> wrote:
> >
> > And I still don't know what a ULP is.
> 
> Upper Layer Protocol.
> 
> That's a generic term for an RDMA verbs consumer, like NVMe or
> RPC-over-RDMA.

No wonder I don't spot what it meant.
I'm guessing you have something specific in mind for RDMA as well.

Don't assume that everyone has read all the high level protocol
specs (and remembers the all the TLA (and ETLA)) when talking
about very low level hardware features.

Especially when you are also referring to how the 'relaxed ordering'
bit of a PCIe write TLP is processed.

This all makes your commit message even less meaningful.

In principle some writel() could generate PCIe write TLP (going
to the target) that have the 'relaxed ordering' bit set.
So a ULP that supports relaxed ordering could actually expect
to generate them - even though there is probably no method
of setting the bit.
Although, in principle, I guess that areas that are 'prefetchable'
(for reads) could be deemed suitable for relaxed writes.
(That way probably lies madness and a load of impossible to fix
timing bugs!)

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)