linux-kernel - [PATCH 19/27] arm64: dts: mt8195: add dp

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20210615173233.26682-19-tinghan.shen@mediatek.com>
Date:   Wed, 16 Jun 2021 01:32:25 +0800
From:   Tinghan Shen <tinghan.shen@...iatek.com>
To:     <robh+dt@...nel.org>, <matthias.bgg@...il.com>
CC:     <devicetree@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <srv_heupstream@...iatek.com>,
        <seiya.wang@...iatek.com>, <wenst@...gle.com>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        Jason-JH Lin <jason-jh.lin@...iatek.com>
Subject: [PATCH 19/27] arm64: dts: mt8195: add dp_intf node

From: Jason-JH Lin <jason-jh.lin@...iatek.com>

add dp_intf cnode

Signed-off-by: Jason-JH Lin <jason-jh.lin@...iatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 31 ++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 0399aa8cf994..560a0583ca0b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2003,6 +2003,29 @@
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
 		};
 
+		dp_intf0: dp_intf0@...15000 {
+			status = "disabled";
+			compatible = "mediatek,mt8195-dpintf";
+			reg = <0 0x1c015000 0 0x1000>;
+			interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0  CLK_VDO0_DP_INTF0>,
+				<&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+				<&topckgen CLK_TOP_EDP_SEL>,
+				<&topckgen CLK_TOP_TVDPLL1_D2>,
+				<&topckgen CLK_TOP_TVDPLL1_D4>,
+				<&topckgen CLK_TOP_TVDPLL1_D8>,
+				<&topckgen CLK_TOP_TVDPLL1_D16>,
+				<&topckgen CLK_TOP_TVDPLL1>;
+			clock-names = "hf_fmm_ck",
+				      "hf_fdp_ck",
+				      "MUX_DP",
+				      "TVDPLL_D2",
+				      "TVDPLL_D4",
+				      "TVDPLL_D8",
+				      "TVDPLL_D16",
+				      "DPI_CK";
+		};
+
 		smi_common0: smi@...1b000 {
 			compatible = "mediatek,mt8195-smi-common";
 			mediatek,common-id = <0>;
@@ -2113,6 +2136,14 @@
 			ddc-i2c-bus = <&hdmiddc0>;
 			status = "disabled";
 		};
+
+		edp_tx: edp_tx@...00000 {
+			status = "disabled";
+			compatible = "mediatek,mt8195-dp_tx";
+			reg = <0 0x1c500000 0 0x8000>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
+			interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+		};
 	};
 
 	hdmiddc0: ddc_i2c {
-- 
2.18.0