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Message-ID: <20210615173233.26682-20-tinghan.shen@mediatek.com>
Date: Wed, 16 Jun 2021 01:32:26 +0800
From: Tinghan Shen <tinghan.shen@...iatek.com>
To: <robh+dt@...nel.org>, <matthias.bgg@...il.com>
CC: <devicetree@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <srv_heupstream@...iatek.com>,
<seiya.wang@...iatek.com>, <wenst@...gle.com>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
Dong Huang <Dong.Huang@...iatek.com>,
Yidi Lin <yidi.lin@...iatek.com>
Subject: [PATCH 20/27] arm64: dts: mt8195: fix nor_flash node
From: Dong Huang <Dong.Huang@...iatek.com>
Fix nor_flash with proper clock for mt8195
Signed-off-by: Dong Huang <Dong.Huang@...iatek.com>
Signed-off-by: Yidi Lin <yidi.lin@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 560a0583ca0b..d78cd4d4201b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1162,8 +1162,12 @@
compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor";
reg = <0 0x1132c000 0 0x1000>;
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
- clock-names = "spi", "sf";
+ clocks = <&topckgen CLK_TOP_SPINOR_SEL>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
+ clock-names = "spi", "sf", "axi";
+ assigned-clocks = <&topckgen CLK_TOP_SPINOR_SEL>;
+ assigned-clock-parents = <&clk26m>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
--
2.18.0
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