linux-kernel - [PATCH 03/27] arm64: dts: mt8195: add pwrap node

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Date:   Wed, 16 Jun 2021 01:32:10 +0800
From:   Tinghan Shen <tinghan.shen@...iatek.com>
To:     <robh+dt@...nel.org>, <matthias.bgg@...il.com>
CC:     <devicetree@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <srv_heupstream@...iatek.com>,
        <seiya.wang@...iatek.com>, <wenst@...gle.com>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        Henry Chen <henryc.chen@...iatek.com>
Subject: [PATCH 03/27] arm64: dts: mt8195: add pwrap node

From: Henry Chen <henryc.chen@...iatek.com>

Add pwrap node to SOC MT8195.

Signed-off-by: Henry Chen <henryc.chen@...iatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 640f09100bb7..bbb1e008e522 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -322,6 +322,18 @@
 			clocks = <&clk26m>;
 		};
 
+		pwrap: pwrap@...24000 {
+			compatible = "mediatek,mt8195-pwrap", "syscon";
+			reg = <0 0x10024000 0 0x1000>;
+			reg-names = "pwrap";
+			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
+			clock-names = "spi", "wrap";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>;
+		};
+
 		uart0: serial@...01100 {
 			compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11001100 0 0x100>;
-- 
2.18.0