linux-kernel - [RFC v1 02/11] clk: qcom: rcg2: Add support for flags

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Date:   Wed, 16 Jun 2021 16:10:58 +0200
From:   Robert Foss <robert.foss@...aro.org>
To:     agross@...nel.org, bjorn.andersson@...aro.org,
        mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
        jonathan@...ek.ca, tdas@...eaurora.org,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Vinod Koul <vinod.koul@...aro.org>
Cc:     Robert Foss <robert.foss@...aro.org>
Subject: [RFC v1 02/11] clk: qcom: rcg2: Add support for flags

These changes are ported from the downstream driver, and are used on SM8350
for CAMCC, DISPCC, GCC, GPUCC & VIDEOCC.

Signed-off-by: Robert Foss <robert.foss@...aro.org>
---
 drivers/clk/qcom/clk-rcg.h  | 4 ++++
 drivers/clk/qcom/clk-rcg2.c | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 99efcc7f8d88..a1f05281d950 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -149,6 +149,10 @@ struct clk_rcg2 {
 	const struct freq_tbl	*freq_tbl;
 	struct clk_regmap	clkr;
 	u8			cfg_off;
+	u8			flags;
+#define FORCE_ENABLE_RCG	BIT(0)
+#define HW_CLK_CTRL_MODE	BIT(1)
+#define DFS_SUPPORT		BIT(2)
 };
 
 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 42f13a2d1cc1..ed2c9b6659cc 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -295,6 +295,9 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
 	if (rcg->mnd_width && f->n && (f->m != f->n))
 		cfg |= CFG_MODE_DUAL_EDGE;
+	if (rcg->flags & HW_CLK_CTRL_MODE)
+		cfg |= CFG_HW_CLK_CTRL_MASK;
+
 	return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
 					mask, cfg);
 }
-- 
2.30.2