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Message-ID: <CAPDyKFpTf8DvauD17JR+jMH1TypgPiNs86k3YtaD4g10fRp65Q@mail.gmail.com>
Date: Thu, 17 Jun 2021 12:04:17 +0200
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Michal Simek <michal.simek@...inx.com>,
Manish Narani <manish.narani@...inx.com>,
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@...inx.com>
Cc: rashmi.a@...el.com, linux-drivers-review-request@...ists.intel.com,
linux-mmc <linux-mmc@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Kishon <kishon@...com>, Vinod Koul <vkoul@...nel.org>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
linux-phy@...ts.infradead.org, Mark Gross <mgross@...ux.intel.com>,
kris.pan@...ux.intel.com, furong.zhou@...el.com,
mallikarjunappa.sangannavar@...el.com,
Adrian Hunter <adrian.hunter@...el.com>,
mahesh.r.vaidya@...el.com, nandhini.srikandan@...el.com,
"Raja Subramanian, Lakshmi Bai"
<lakshmi.bai.raja.subramanian@...el.com>
Subject: Re: [“PATCH” 1/2] mmc: sdhci-of-arasan: Use clock-frequency property to update clk_xin
On Fri, 4 Jun 2021 at 08:13, Michal Simek <michal.simek@...inx.com> wrote:
>
>
>
> On 6/3/21 8:22 PM, rashmi.a@...el.com wrote:
> > From: Rashmi A <rashmi.a@...el.com>
> >
> > If clock-frequency property is set and it is not the same as the current
> > clock rate of clk_xin(base clock frequency), set clk_xin to use the
> > provided clock rate.
> >
> > Signed-off-by: Rashmi A <rashmi.a@...el.com>
> > Reviewed-by: Adrian Hunter <adrian.hunter@...el.com>
> > ---
> > drivers/mmc/host/sdhci-of-arasan.c | 14 ++++++++++++--
> > 1 file changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> > index 839965f7c717..0e7c07ed9690 100644
> > --- a/drivers/mmc/host/sdhci-of-arasan.c
> > +++ b/drivers/mmc/host/sdhci-of-arasan.c
> > @@ -1542,6 +1542,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
> > }
> > }
> >
> > + sdhci_get_of_property(pdev);
> > +
> > sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
> > if (IS_ERR(sdhci_arasan->clk_ahb)) {
> > ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
> > @@ -1561,14 +1563,22 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
> > goto err_pltfm_free;
> > }
> >
> > + /* If clock-frequency property is set, use the provided value */
> > + if (pltfm_host->clock &&
> > + pltfm_host->clock != clk_get_rate(clk_xin)) {
> > + ret = clk_set_rate(clk_xin, pltfm_host->clock);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Failed to set SD clock rate\n");
> > + goto clk_dis_ahb;
> > + }
> > + }
> > +
> > ret = clk_prepare_enable(clk_xin);
> > if (ret) {
> > dev_err(dev, "Unable to enable SD clock.\n");
> > goto clk_dis_ahb;
> > }
> >
> > - sdhci_get_of_property(pdev);
> > -
> > if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
> > sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
> >
> >
>
> Manish/Sai: Please retest this on Xilinx SOC.
>
> Thanks,
> Michal
I am about to queue this patch, but it would be nice to get your
confirmation and tested-by tags before doing so. Would that be
possible within the next couple of days?
Kind regards
Uffe
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